Chang Yong Kang

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.

Optimized NH/sub 3/ annealing Process for high-quality HfSiON gate oxide

Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600/spl deg/C, 40 s NH/sub 3/ PDA, showed superior I/sub d/--V/sub d/ (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.

Effects of varying interfacial oxide and high-k layer thicknesses for HfO2 metal–oxide–semiconductor field effect transistor

A metal–oxide–semiconductor capacitor and field effect transistor with a hafnium oxide (HfO2) dielectric have been fabricated. Various thicknesses of interfacial oxide and HfO2 film have been used. The results show that the flatband voltage changed due to the change in the physical thickness of the HfO2 film, and not that of the interfacial oxide layer. In addition, the effective channel electron mobility depends on both the amount of fixed charges and the distance from the fixed charges to the Si surface. The results also suggest that the fixed charges are rather uniformly distributed throughout the bulk of high-k layer.

Nickel-silicide phase effects on flatband voltage shift and equivalent oxide thickness decrease of hafnium silicon oxynitride metal-silicon-oxide capacitors

This Letter reports the nickel-silicide phase effects on the electrical characteristics of high-k and silicon dioxide (SiO2) metal-oxide-semiconductor devices. It was found that the silicon-deficient nickel-silicided gate electrode on the hafnium silicon oxynitride (HfSiON) led to a positive flatband voltage (Vfb) shift and a reduction in the equivalent oxide thickness (EOT). However, negligible Vfb shift and EOT decrease were observed in the case of control hafnium oxide and SiO2 structures. It was believed that Si dissociation from the HfSiON layer was the main reason for the positive Vfb shift and the EOT decrease.

Hafnium Titanate bilayer structure multimetal dielectric nMOSCAPs

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bilayer multimetal oxide dielectric has been developed for high-performance CMOS applications. Ultrathin equivalent oxide thickness (/spl sim/8 /spl Aring/) has been achieved with increased effective permittivity (k/spl sim/36). Hysteresis was significantly reduced using the bilayer dielectric. Top TiO/sub 2/ layer was found to induce effective negative charge from the flatband voltage shift. Leakage current characteristic was slightly higher than control HfO/sub 2/, and this is believed to be due to the lower band offset of TiO/sub 2/. However, the interface state density of this bilayer structure was found to be similar to that of HfO/sub 2/ MOSCAP because the bottom layer is HfO/sub 2/. These results demonstrate the feasibility of new multimetal dielectric application for future CMOS technology.

Improved electrical and material characteristics of HfTaO gate dielectrics with high crystallization temperature

N-type metal-oxide-semiconductor field-effect transistors (N-MOSFETs) using HfTaO with varying Ta composition (20%, 30%, 40%, and 50%) have been fabricated and characterized. Crystallization temperatures of HfTaO with varying Ta composition were also measured. It was found that HfTaO with 40% Ta exhibited the highest crystallization temperature of 900u2009°C, while 35% and 52% HfTaO showed crystallization temperature of 800u2009°C. The results demonstrate that HfTaO N-MOSFETs exhibit higher electron mobility than controlled HfO2 devices. Among them, the transistor with 40% Ta shows the highest electron mobility.

Positive bias temperature instability effects of Hf-based nMOSFETs with various nitrogen and silicon profiles

Positive bias temperature instability (PBTI) effects of HfO/sub 2/-based nMOSFETs with various nitrogen profiles in HfO/sub 2/ were investigated. The nitrogen profile was modulated by an inserting Si layer (/spl sim/6/spl Aring/) into hafnium oxynitride gate dielectrics. The Si layer is used to trap nitrogen and to suppress nitrogen out-diffusion during subsequent anneals. Compared to control HfO/sub x/N/sub y/ without Si insertion, the Si-inserted HfO/sub x/N/sub y/ samples exhibited reduced PBTI degradation, especially if the Si layer was placed further from the Si interface. The improvement can be attributed to the reduction of oxide bulk trapped as well as reduced interface trapped charge generation resulting from compensation effect of inserted Si layer.

Effects of tantalum penetration through hafnium oxide layer on carrier generation rate in silicon substrate and carrier mobility degradation

This letter presents the effects of tantalum penetration through hafnium oxide on bulk carrier generation rates and carrier mobility degradation. The penetration of Ta atoms degraded the bulk carrier lifetime in the Si substrate. Surface nitrogen incorporation can be useful to mitigate Ta penetration into the Si substrate. The incorporated Ta in the dielectric was found to have no effect on the effective κ value. On the other hand, it increased pre-existing traps and interface states. Thus, mobility degradation for tantalum nitride gate devices was primarily caused by pre-existing traps and interface states of the high-k dielectrics.

Effects of dielectric structure of HfO2 on carrier generation rate in Si substrate and channel mobility

This letter presents the effects of surface preparation for hafnium-based dielectrics on the bulk carrier generation rates and the carrier mobility. Different surface preparations result in different interfacial layers. Nitrogen-incorporated layers effectively block impurity penetration from hafnium oxide, and lead to the increase of bulk carrier generation lifetime. However, nitrogen-incorporated interface layers increase interface state density and degrade channel mobility, even though bulk carrier generation lifetime is increased. Thus, mobility degradation is preliminarily caused by fixed charge and interface states of the high-k dielectrics.

Transient bicarrier response in high-k dielectrics and its impact on transient charge effects in high-k complementary metal oxide semiconductor devices

In this letter, transient charge trapping and detrapping characteristics in high-k n∕p metal oxide semiconductor field effect transistors (MOSFETs) were studied. Transient charge trapping was found to be an interface thickness-limited phenomenon. Additionally, transient trapping of electrons, rather than holes, was found to be dominant even in pMOSFETs. Transient charge recombination or bicarrier response within the high-k layer was the main reason for the dependence on input signal in high-k devices. Detrapping characteristics for nMOSEFTs and pMOSFETs were correlated to the transient hole and electron trappings, respectively.