Cheng-Chuan Huang

5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

25 nm CMOS Omega FETs

Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 /spl mu/A//spl mu/m and 780 /spl mu/A//spl mu/m with off state leakage currents of 8 nA//spl mu/m and 0.4 nA//spl mu/m for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 /spl mu/A//spl mu/m for N-FET and 550 /spl mu/A//spl mu/m for P-FET at an off current of 1 /spl mu/A//spl mu/m. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections.

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Scaling of CMOS FinFETs towards 10 nm

CMOS FinFETs with 35 nm gate length L/sub g/ and performance parameters exceeding that of ITRS projections are fabricated. Device simulations are performed to match the experimental results and to explore the scalability and optimization of FinFETs to 10 nm gate length. Symmetrical NMOS and PMOS V/sub t/s, low off-state leakages, and high drive currents can be realized using dual-doped poly-Si or mid-gap gate electrodes.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

Modeling isolation-induced mechanical stress effect on SOI MOS devices

In this paper, the mechanical stress effect of SOI MOS devices was analysed. The width dependence of stress effect and drain current shift were evaluated.