Hou-Yu Chen

5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.

Study of a Nanoparticle Charger Containing Multiple Discharging Wires in a Tube

Abstract A unipolar charger containing multiple discharging wires in a tube (inner diameter: 50 mm) was developed and tested in order to increase the aerosol flow rate and the charging efficiency of nanoparticles. Four gold wires of 25 µm in diameter and 15 mm in length were used as the discharging electrodes to generate positive ions (Ni) from 2.72 × 108 ions/cc to 3.87 × 109 ions/cc in concentration at the discharging voltage of + 4.0 ∼ + 10 KV. Monodisperse NaCl particles of 10 ∼ 50 nm in diameter were used to test the charging efficiency and the particle loss of charged particles with different aerosol flow rates, corona voltages and sheath flow rates. The sheath air near the tube wall was found to increase the extrinsic charging efficiency, and the highest efficiency was obtained at + 6.0 KV discharging voltage, 10 L/min aerosol flow rate and 9 L/min sheath flow rate. The extrinsic charging efficiency increased from 10.6% to 74.2% when the particle diameter was increased from 10 to 50 nm. The TDMA (tandem differential mobility analyzer) method was used to determine the charge distribution and the mean charge per particle and it was found that the Fuchs charging theory corrected for the extrinsic charging efficiency matched with the experimental data very well.

16nm functional 0.039µm 2 6T-SRAM cell with nano injection lithography, nanowire channel, and full TiN gate

Record area size of 0.039µm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR). The NIL technique is not only maskless for minimizing entry cost but also photoresist free to greatly enhance pattern resolution, down to 2nm 3-sigma line width roughness, and without significant proximity effect. Devices with nanowire channels and full TiN single gate for both N- and P-MOS are demonstrated with short channel and simplified integration process. This work discloses a new way to explore 16nm CMOS device and circuit design, and obtains early access to extreme CMOS scaling.

Nickel Silicide Formation using Pulsed Laser Annealing for nMOSFET Performance Improvement

The formation of a uniform, high tensile stress and low silicide/Si interfacial resistance nickel silicide in nMOSFET by introducing pulsed laser annealing (PLA) is reported. This annealing approach facilitated the phase transformation of nickel silicide to Si-rich NiSix compounds using a low-thermal-budget process, improves the silicide/Si interface regularity and avoids familiar (111) NiSi2 facet formation at a laser energy of 1.5 J cm � 2 . By increasing laser energy density up to 2.3 J cm � 2 , the device performance and statistics junction leakage distribution were degraded due to the increased sheet resistance of silicide layer and the destroyed silicide/Si interface morphology. When the PLA with a laser energy density of 1.5 J cm � 2 was employed for nickel silicidation on the p-type Schottky diodes, a 0.16 eV hole Schottky barrier height (SBH) increase from 0.52 to 0.68 eV was observed. In addition, the

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

For more than 45 years, photon- and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 μm2), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic Vdd regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.