Kerem Akarvardar

Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI

In this work, we report high performance (I<inf>on</inf> ∼1 mA/µm at Ioff 100nA/µm @ 1V Vcc) short channel p-type SiGe/Si FinFETs combining high mobility, low T<inf>inv</inf> (scaled High-k w/o Si cap), low R<inf>sd</inf>, and process-induced strain. A dual channel scheme for high mobility CMOS FinFETs is demonstrated.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Impact of Fin Doping and Gate Stack on FinFET (110) and (100) Electron and Hole Mobilities

Double-gate FinFET (110) (110) and (100) (100} electron mobility (μ_e) and hole mobility (μ_h) are experimentally investigated for the following: 1) a wide range of boron and phosphorus fin doping concentrations and 2) a wide variety of gate stacks combining HfO₂, SiO₂, or SiON insulators with TiN or poly-Si electrodes. It is found out that, irrespective of fin doping and gate stack, (110) (110) μ_e is competitive with the (100)(100) μ_e, while (110)(110) μ_h is ≥ 2× higher than (100) (100) μ_h. Inversion μ_e and μ_h are independent of doping as long as the effective field/doping combination enables the screening of the depletion charge. Mobility degradation with doping is significantly lower in accumulation mode (AM) than in inversion mode (IM) such that, for heavily B-doped fins, AM hole mobility exceeds the IM electron mobility even in (100) FinFETs. In undoped fins, ALD TiN gate stress is observed to improve μ_e for both orientations without degrading μ_h.

Enhanced performance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node

We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate stacks. These attributes constitute a simple non-planar cMOS integration sequence for enhancing future high performance technology nodes.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Performance and variability in multi-V T FinFETs using fin doping

The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ~25 nm, >;1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation mode FinFETs. A VT modulation of ±0.25 V using fin B and P doping comes at the expense of 24% and 14% high field mobility penalty for NFET and PFET, respectively. For the same dose, Arsenic is found to modulate the VT more effectively than does Phosphorus. Basic modeling results show that for aggressively scaled (5 nm-wide) fins, the impact of single dopant atom on VT can be as high as 25 mV, severely challenging the viability of the technique towards the end of roadmap.

Physical insights on comparable electron transport in (100) and (110) double-gate fin field-effect transistors

We have investigated the physical mechanisms that result in comparable electron mobility measured from (100) and (110) sidewall double-gate fin field-effect transistors (FinFETs). Using a self-consistent Schrodinger-Poisson simulator coupled with a sp3d5s* tight-binding bandstructure, we have shown that the (100)/〈100〉 and (110)/〈110〉 average conductivity effective mass values are similar. This is explained by the much heavier non-parabolic confinement mass for Δ2 valley of (110) FinFETs, which leads to lower Δ2 energy than Δ4. Thus, for both (100) and (110), the majority of electrons occupy the Δ2 valley with 0.19m0 conductivity effective mass, resulting in comparable electron mobility.

Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling

In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.

Understanding the FinFET Mobility by Systematic Experiments

The impact of the surface orientation, strain, fin doping, and gate stack on SOI double-gate FinFET mobility is systematically investigated. Impact of channel material, temperature, and fin width were also touched upon to better understand the trends. For the unstrained case, the (110) sidewall electron mobility is very close to the (100) sidewall electron mobility irrespective of the fin doping level and gate stack. This weak dependence of electron mobility to surface orientation distinguishes the FinFETs from the bulk planar MOSFETs, where (100) electron mobility is systematically reported to be much higher than that of (110). On the other hand, the (110) sidewall hole mobility is substantially higher than the (100) sidewall hole mobility in FinFETs, as in the planar case. Both the (100)/ and (110)/ FinFET electron mobility can be improved with tensile strain. It is also confirmed that the (110)/ FinFET hole mobility can be significantly improved with compressive strain while the (100)/ hole mobility is sensitive to neither compressive nor tensile strain. Compared to Si, the use of a SiGe channel increases the hole mobility drastically, and even further improvement is achievable by external compressive stress. Overall, the experimental results in this chapter suggest that the (110)/ Si FinFETs conventionally built on standard (100) wafers offer simultaneously high electron and hole mobility, which can be further improved by tensile and compressive stress, respectively.

Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs

Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak G_m and I_Dsat, however also higher I_off than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO₂ gate and NiPtSi S/D achieve I_Dsat = 0.8 mA/um and I_on/I_off >; 2000 for VGS = -1.5 V, V_DS = -1 V, and 100 nm nanowire length.