S. Athanasiou

Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four-Gate MOSFET

The supercoupling effect is demonstrated experimentally by monitoring the electron and hole currents in a field-effect transistor provided with p+ and n+ contacts. According to the polarity of the voltage applied to the front and back gates, only electrons or holes can be detected in 7-nm thick silicon layers. Thicker layers are not affected by supercoupling and can accommodate electrons and holes together.

Impact of back plane on the carrier mobility in 28nm UTBB FDSOI devices, for ESD applications

We present measurements and parameter extraction performed on 28nm UTBB FDSOI MOSFETs with two different Back Plane configurations (p-type and n-type BP). The change in BP doping and work function affects directly the back-channel characteristics and indirectly, via interface coupling, the front-channel properties. We investigate the parameters relevant for the design of ESD protection devices: threshold voltage shift and electron mobility in long and short transistors.

Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology

The purpose of this paper is to analyze the ESD device electro-thermal behavior of BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope (AVS) method). We show how the series resistance and the thermal resistance impact the average and peak temperatures in these devices.

GDNMOS: A new high voltage device for ESD protection in 28nm UTBB FD-SOI technology

We propose a novel device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation, in particular in thyristor mode. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Preliminary results on TFET — Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology

The purpose of this paper is to introduce preliminary results on thin silicon film TFET (gated diode) topology in 28 nm FD-SOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models and on silicon measurements of different devices. It shows that the TFET is functional and could be enhanced for advanced IO and ESD design solutions.

Key parameters of BiMOS ESD protection device for UTBB FDSOI advanced technology

We investigate the impact of carrier mobility on the performance of a novel Bipolar MOS (BiMOS) device fabricated in Ultra-Thin Body & BOX (UTBB) FDSOI technology. BiMOS transistor combines bipolar and MOS mechanisms that are trigerred by front-gate, back-gate and body biasing. The device response was studied under Average Current Slope (ACS) stress. The mobility value, which depends on channel material and ground-plane implants, primarily affects the breakdown voltage and the device self-heating.