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Journal of Vacuum Science and Technology | 1996

Surface barrier detection in plasma‐enhanced chemical vapor deposition oxides

Jerris H. Peavey; Robert Dawson; John K. Lowell

The performance standards of plasma‐enhanced chemical vapor deposition (PECVD) oxides increase as device sizes shrink and densities increase for ULSI. Future PECVD dielectric quality may be compromised by the effects of contaminants and/or charged ionic species that are present in the gaseous ambient which the wafers are exposed to. As a result of being left at the oxide/silicon interface, these gaseous ambient defects such as metallic ions can adversely effect reliability and performance. Moreover different types of PECVD oxides require different deposition chemistries and are grown to differing thicknesses making it difficult to apply a single C–V test. In this article, the problem is addressed by detecting, nondestructively, such residual interfacial charge postprocessing on product wafers rather than the traditional test wafers. For the first time the effects of mobile ions and interface states at the oxide/silicon interface and in the as‐processed films for various PECVD oxides will be shown using no electrical test methods before and after anneal. Charge effects and approximate generation lifetime estimates are separated out from the total charge measurement using passive high‐injection surface photovoltage. Thus one can passively examine the induced surface barrier height and interface charge for any PECVD oxide type at any thickness. This technique is demonstrated for several types of single‐oxide samples. The charge effects (if any) in PECVD oxides as‐deposited with or without rapid thermal annealing treatments are illustrated.The performance standards of plasma‐enhanced chemical vapor deposition (PECVD) oxides increase as device sizes shrink and densities increase for ULSI. Future PECVD dielectric quality may be compromised by the effects of contaminants and/or charged ionic species that are present in the gaseous ambient which the wafers are exposed to. As a result of being left at the oxide/silicon interface, these gaseous ambient defects such as metallic ions can adversely effect reliability and performance. Moreover different types of PECVD oxides require different deposition chemistries and are grown to differing thicknesses making it difficult to apply a single C–V test. In this article, the problem is addressed by detecting, nondestructively, such residual interfacial charge postprocessing on product wafers rather than the traditional test wafers. For the first time the effects of mobile ions and interface states at the oxide/silicon interface and in the as‐processed films for various PECVD oxides will be shown using no...


Microelectronic device technology. Conference | 1997

Device performance and optimization for 5th- and 6th-generation microprocessors

Bijnan Bandyopadhyay; Jon D. Cheek; Robert Dawson; Michael Duane; Jim Fulford; Mark I. Gardner; Fred N. Hause; Bernard W. K. Ho; Daniel Kadoch; Raymond T. Lee; Ming-Yin Hao; Chuck May; Mark W. Michael; Brad T. Moore; Deepak K. Nayak; John L. Nistler; Dirk Wristers

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.


Archive | 1997

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Robert Dawson; Mark W. Michael; Basab Bandyopadhyay; H. Jim Fulford; Fred N. Hause; William S. Brennan


Archive | 1994

Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate

Robert Dawson; Kenneth J. Ponder


Archive | 1996

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

H. Jim Fulford; Robert Dawson; Fred N. Hause; Basab Bandyopadhyay; Mark W. Michael; William S. Brennan


Archive | 1997

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Mark I. Gardner; Robert Dawson; H. Jim Fulford; Frederick N. Hause; Daniel Kadosh; Mark W. Michael; Bradley T. Moore; Derick J. Wristers


Archive | 1997

Method of making NMOS and PMOS devices with reduced masking steps

Frederick N. Hause; Robert Dawson; H. Jim Fulford; Mark I. Gardner; Mark W. Michael; Bradley T. Moore; Derick J. Wristers


Archive | 1998

Interlevel dielectric with air gaps to lessen capacitive coupling

Basab Bandyopadhyay; H. Jim Fulford; Robert Dawson; Fred N. Hause; Mark W. Michael; William S. Brennan


Archive | 1997

Method and apparatus for in situ anneal during ion implant

Robert Dawson; H. Jim Fulford; Mark I. Gardner; Frederick N. Hause; Mark W. Michael; Bradley T. Moore; Derick J. Wristers


Archive | 1997

Method of channel doping using diffusion from implanted polysilicon

H. Jim Fulford; Robert Dawson; Mark I. Gardner; Frederick N. Hause; Mark W. Michael; Bradley T. Moore; Derick J. Wristers

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