Cheng-chieh Hsieh

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

Reliability evaluation of a CoWoS-enabled 3D IC package

TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. The stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoS™-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermo-mechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.

Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications

Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using a specially designed thermal test vehicle. Two competing technologies, flip-chip PoP (FC_PoP) and 3DIC, are also included in this study as the reference for thermal performance benchmark. Direct thermal performance comparison is made possible by the data collected on the comparable FC_PoP thermal test vehicles. Thermal models have been successfully developed to enable further study on the cross-package performance comparison, as well as the impact of various key package design parameters. With the innovative approach replacing the organic substrate with thermally favorable RDL layers, a typical InFO_PoP package has 12% and 17% lower junction-to-ambient thermal resistance than a typical FC_PoP and 3DIC package, respectively. The appealing transient thermal response also makes the InFO_PoP the most competitive 3D packaging technology in high-performance mobile applications. Although the strong thermal interactions between the component packages of a PoP package complicates the thermal analysis, power envelop is proposed and demonstrated as a useful tool for package thermal design optimization. In addition, transient thermal analysis is recommended as a supplementary thermal design approach to the commonly used steady-state thermal analysis.