Ching-Yi Wu

3D 65nm CMOS with 320°C microwave dopant activation

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing

Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120°C to 140°C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150°C reduction in maximum temperature at the same activation concentration (about 2 × 1019 cm-3) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300degC-500degC. By using a low-temperature microwave anneal, the sheet resistance and boron diffusion in the Si/Ge/Si substrate could be reduced effectively, and the crystalline structure of Si/Ge/Si is not damaged according to the TEM image and the XRD signals.

Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing

Microwave annealing of dopants in Si has been re ported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 × 1015 ion/cm2, were annealed by microwave methods at temperatures below 500°C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.

Susceptor Coupling for the Uniformity and Dopant Activation Efficiency in Implanted Si Under Fixed-Frequency Microwave Anneal

Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, during conventional fixed-frequency microwave heating, standing wave patterns can be established in the microwave processing chamber, resulting in nodes and antinodes over the processing area, resulting in thermal variations over the process wafer. In this letter, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency microwave anneal are studied. The composition, number, and spacing of susceptor wafers were varied in a systematic fashion in these experiments.

Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased Cox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.

Fabrication and Characterization of a Three-Dimensional Flexible Thermopile

This paper presents the fabrication and characterization of a three-dimensional (3D) thermopile; consists of 71 Cu–Ni series-connected thermocouples on polyimide (PI) flexible substrate. Using wet etching to etch through 25 µm PI, the cold and hot junctions of thermocouples are formed on the top and bottom surfaces of PI substrate. This 3D layout design differentiates its innovative uniqueness from the traditional 2D planar thermopiles that have both hot and cold junctions on the same plane. The experimental studies on the PI etching with respect to the concentrations of KOH and C2H7NO in the etching solution conclude that the optimal composition of the etchant is 7–9 M KOH with 2–4 M C2H7NO and etched at 80 °C. A measured sensitivity of 0.44 mV/K is realized in the fabricated device. The temperatures measured by the 3D thermopile are very close to those obtained with a digital thermometer, demonstrating that 3D flexible thermopiles has great potential to provide low cost thermal sensor.

Computer-generated holographic diffuser for color mixing

An iterative algorithm for multiple incoming wavelengths is proposed to design a computer-generated holographic diffuser with the features of high light utilization efficiency and uniform color mixing. The amplitude transmittance of this computer-generated holographic diffuser is constant, while the phase transmittance consists of multiple phase levels. This diffuser is designed according to the Fraunhofer diffraction theory and can uniformly spread the different input light at the same time. The simulation results show that over 88% average far field amplitude transmission efficiency is achieved for each input light and the output uniformity is within 12.4%.

Fabrication of the planar angular rotator using the CMOS process

This investigation proposes a novel planar angular rotator fabricated by the conventional CMOS process. Following the 0.6 /spl mu/m SPTM (single poly triple metal) CMOS process, the device is completed by a simple post-process with maskless etching. The suspension unit rotates around its geometric center with electrostatic actuation. In addition to having a single rotatory component, 2/spl times/2 and 3/spl times/3 arrayed components are designed to have a larger rotatory angle with less actuation distance. The proposed design adopts an intelligent mechanism, including slider-crank and four-bar linkage, to permit simultaneous motion. With driving voltages of around 40 volts, the CMOS planar angular rotator could be driven. Comparing to the most common planar angular, micromotor, the design proposed herein has a shorter response time and longer life without the problems of friction and wear.