Fu-Kuo Hsueh

3D 65nm CMOS with 320°C microwave dopant activation

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing

Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120°C to 140°C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150°C reduction in maximum temperature at the same activation concentration (about 2 × 1019 cm-3) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300degC-500degC. By using a low-temperature microwave anneal, the sheet resistance and boron diffusion in the Si/Ge/Si substrate could be reduced effectively, and the crystalline structure of Si/Ge/Si is not damaged according to the TEM image and the XRD signals.

Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing

Microwave annealing of dopants in Si has been re ported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 × 1015 ion/cm2, were annealed by microwave methods at temperatures below 500°C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (~ 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. ~ 67mV/dec) and excellent on-off ratio (>106) for both n and p channel devices. Threshold voltage (VTH) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.

Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks

In this letter, low-temperature (480°C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.

Susceptor Coupling for the Uniformity and Dopant Activation Efficiency in Implanted Si Under Fixed-Frequency Microwave Anneal

Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, during conventional fixed-frequency microwave heating, standing wave patterns can be established in the microwave processing chamber, resulting in nodes and antinodes over the processing area, resulting in thermal variations over the process wafer. In this letter, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency microwave anneal are studied. The composition, number, and spacing of susceptor wafers were varied in a systematic fashion in these experiments.

Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and Ultrathin 7.5nm Ni mono-germanide

For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased Cox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.