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Dive into the research topics where Christopher D. Sheraw is active.

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Featured researches published by Christopher D. Sheraw.


Ibm Journal of Research and Development | 2011

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer; G. Freeman; Colin J. Brodsky; Anthony I. Chou; D. Corliss; Sameer H. Jain; Naftali E. Lustig; Vincent J. McGahay; Shreesh Narasimha; James P. Norum; Karen A. Nummy; Paul C. Parries; Sujatha Sankaran; Christopher D. Sheraw; P. R. Varanasi; Geng Wang; M. E. Weybright; Xiulan Yu; E.F. Crabbe; Paul D. Agnello

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.


Proceedings of SPIE, the International Society for Optical Engineering | 2006

Silicon containing polymer in applications for 193 nm high NA lithography processes

Sean D. Burns; Dirk Pfeiffer; Arpan P. Mahorowala; Karen Petrillo; Alexandera Clancy; Katherina Babich; David R. Medeiros; Scott D. Allen; Steven J. Holmes; Michael M. Crouse; Colin J. Brodsky; Victor Pham; Yi-Hsiung Lin; Kaushal S. Patel; Naftali E. Lustig; Allen H. Gabor; Christopher D. Sheraw; Phillip J. Brock; Carl E. Larson

The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC. To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.


Archive | 2008

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Herbert L. Ho; Mahender Kumar; Qiqing Ouyang; Paul A. Papworth; Christopher D. Sheraw; Michael D. Steigerwalt


Archive | 2008

VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION

Herbert L. Ho; Mahender Kumar; Qiging Ouyang; Paul A. Papworth; Christopher D. Sheraw; Michael D. Steigerwalt


Archive | 2005

STRUCTURE AND METHOD FOR IMPROVED DIODE IDEALITY

Edward P. Maciejewski; Sherry A. Womack; Shreesh Narasimha; Christopher D. Sheraw


Archive | 2014

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Bhupesh Chandra; Paul Chang; G. Freeman; Dechao Guo; Judson R. Holt; Arvind Kumar; Timothy J. McArdle; Shreesh Narasimha; Viorel Ontalus; Sangameshwar Rao Saudari; Christopher D. Sheraw; Matthew W. Stoker


Archive | 2006

Decoder for a Stationary Switch Machine

Yun-Yu Wang; Christopher D. Sheraw; Anthony G. Domenicucci; Linda Black; Judson R. Holt; David M. Fried


Archive | 2006

COPPER CONTACT VIA STRUCTURE USING HYBRID BARRIER LAYER

Randolph F. Knarr; Christopher D. Sheraw; Andrew H. Simon; Anna W. Topol; Yun-Yu Wang; Keith Kwong Hon Wong


Archive | 2008

METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES

David M. Dobuzinsky; Thomas S. Kanarsky; Munir D. Naeem; Christopher D. Sheraw; Richard S. Wise


Archive | 2006

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

Herbert L. Ho; Mahender Kumar; Qiqing Ouyang; Paul A. Papworth; Christopher D. Sheraw; Michael D. Steigerwalt

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