Linda Black

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi:C strain. Acknowledgements This work was performed by IBM/AMD/Freescale Alliance Teams at various IBM Research and Development Facilities. We wish to thank Applied Materials and ASM America for supplying high quality eSi:C EPI materials. References: [1] Kah-Wee Ang, King-Jien Chui, Vladimir Bliznetsov, Yihua Wang, Lai-Yin Wong, Chih-Hang Tung, N. Balasubramanian, Ming-Fu Li, Ganesh Samudra, and Yee-Chia Yeo, IEDM Tech. Dig., p503, 2005.[2] Yaocheng Liu, Oleg Gluschenkov, Jinghong Li, Anita Madan, Ahmet Ozcan, Byeong Kim, Tom Dyer, Ashima Chakravarti, Kevin Chan, Christian Lavoie, Irene Popova, Teresa Pinto, Nivo Rovedo, Zhijiong Luo, Rainer Loesing, William Henson, Ken Rim, Symp. on VLSI Tech., p.44, 2007. [3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, B. White, SOI Conf. Proc., p.17, 2007. [4] Zhibin Ren, G. Pei, J. Li, F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J. W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, I. Lauer, D.-G. Park, D. Sadana, and G. Shahidi, Symp. on VLSI Tech., P. 172-173, 2008. [5] A. Madan, J. Li, Z. Ren, F. Yang, E. Harley, T. Adam, R. Loesing, Z. Zhu, T. Pinto, A. Chakravarti, A. Dube, R. Takalkar, J. W. Weijtmans, L. Black, D. Schepis, ECS SiGe and Realted Materials and Devices Symposium, Hawaii, Oct. 2008 (to be published).

Effect of Ion Implantation and Anneals on Fully-strained SiC and SiC:P Films using Multiple Characterization Techniques

In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement [1-3]. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. μXRD strain measurements and SIMS (C and P content) were performed on reference test macros on patterned lithographic wafers. μXRD strain measurements (related to substitutional C) of the asdeposited SiC films show that the C is lower than the actual C suggesting that there is interstitial C in the film. After M1 device measurements, Nanobeam Diffraction (NBD) analysis to determine channel strain was done on selected samples. An in-line μXRD system was used to monitor the strain and thickness variation of the SiC stressor with critical processing steps. Typical uXRD measurements demonstrate that there is a depth profile for the crystalline integrity of the SiC stressor films. The top surface which is in the implant range shows no strain (amorphization due to implants) compared to the fully strained, deeper regions (Fig 1). Figure 2 shows a typical cross-sectional TEM image and NBD patterns with the as-deposited SiC embedded in the source and drain. After M1 device measurements, good correlation was seen between the NBD and uXRD measurements (Fig 3). Stressor strain for samples 1-4 was retained after complete processing. Sample 5 which saw a high temperature anneal showed a complete loss of strain. This correlated well with the device results [4]. Full characterization has helped identify process integration schemes which give significant drive current enhancements [4].