Christopher J. Gonzalez

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

POWER8™ is a 12-core processor fabricated in IBMs 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

Power optimization methodology for the IBM POWER7 microprocessor

Meeting the power budget of the 8 four-way simultaneous multithreading core IBM POWER7® microprocessor without compromising the aggressive performance targets presented a considerable challenge to the design team. Major innovations in the power modeling and power reduction methodologies have been introduced at all levels of the design, including microarchitecture, logic, circuits, postlayout tuning, and technology optimizations. In order to use effectively design resources available for power reduction, the team needed to understand precisely where the power was spent and the sensitivity to design parameters. A new power modeling methodology was deployed that allowed the team to evaluate the impact of design changes and various power reduction actions before sending them to the designers.

IBM POWER7+ design for higher frequency at fixed power

The IBM POWER7+™ microprocessor is the next-generation IBM POWER® processor implemented in IBMs 32-nm silicon-on-insulator process. In addition to enhancing the chip functionality, implementing core-level and chiplet-level power gating and significantly increasing the size of the on-chip cache, the chip achieves a frequency boost of 15% to 25% compared with its predecessor at the same power. To achieve these challenging goals and deliver a serviceable power-frequency limited yield (PFLY), the IBM team made significant innovations in the post-silicon hardware-tuning methodology to counteract the inherent process variability and developed new PFLY models that account for several sources of variability in power and frequency. The paper describes the new methodology and the models, provides analysis of the sources of variability and their impact on power and frequency, and describes the work done to achieve correlation between the models and hardware measurements.

The POWER8 TM processor: Designed for big data, analytics, and cloud environments

POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and todays exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open ecosystem for server innovation.

Sram Operational Voltage Shifts in the Presence of Gate Oxide Defects in 90 NM SOI

The continued scaling of gate oxide thickness in CMOS transistors has made dielectric integrity paramount to system functionality at low voltages. In this paper, the effect of gate oxide breakdown on the minimum operating voltage (Vddmin) of a six transistor SRAM cell has been examined. A new cell reliability model was developed to explain non-monotonic operational voltage shifts through product reliability stress. Through simulation it was determined that non-monotonic voltage shifts can occur if random gate defects counter existing SRAM cell asymmetries. Furthermore, it has been shown that monotonic voltage shifts can be created with significantly different magnitudes of gate oxide defects

IBM POWER8 circuit design and energy optimization

The IBM POWER8™ processor is a 649-mm

5.1 POWER8 TM : A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth

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Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

, 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays.

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4

The 12-core 649mm2 POWER8™ leverages IBMs 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5-80nm, 2-144nm, 3-288nm, and 3-640nm pitch layers for low-latency communication as well as 2-2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks.

High-performance digital subcommittee

We introduce a generalized, efficient, and accurate power abstraction model and generation techniques for complex IP blocks. This is based on the contributor based power modeling concept, which exploits the nature of power consuming components in a design being inherently separable. The generated power abstraction is Process, Voltage and Temperature (PVT) independent, thus enabling very efficient hierarchical power analysis. Our approach constitutes the industrys first design methodology to automatically generate PVT independent contributor based abstracts. We also describe extensions to the power contributor concept to model dynamic power. Extensive analysis and results on real industry designs to study the accuracy impacts of abstraction as a function of design types and sizes are presented. We also present model to hardware correlation experiments demonstrating the application of this abstraction based methodology on the IBM Power7+ server microprocessor chip.