Norman J. Rohrer

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.

A 580 MHz RISC microprocessor in SOI

A RISC microprocessor remapped in SOI technology exploits the advantages of SOI to boost processor frequency by 20% to 580MHz at 2.0V and 85/spl deg/C and fast process. The separation by implanted oxygen (SIMOX) SOI process produces partially-depleted devices. Source and drain capacitances are reduced by an order of magnitude, improving gate delay by 12%. Reduction in body-bias effects on device stacks and passgate topologies results in an additional 15%-25% improvement. Speed gains of up to 35% are achieved in some designs. The frequency-limiting paths in this processor are dominated by SRAM access and self-timed dynamic circuits whose timing had to be relaxed to guarantee functionality.

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

PowerTune is a power-management technique for a multi-gigahertz superscalar 64b PowerPC/sup /spl reg// processor in a 90nm technology. This paper discusses the challenges and implementation of a dynamically controlled clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system.

PowerPC 970 in 130 nm and 90 nm technologies

A 64 b PowerPC microprocessor is introduced in 130 nm and redesigned in 90 nm SOI technology. PowerPC 970 implements a SIMD instruction set with 512 kB L2 cache. It runs at 2.0 GHz with a 1.0 GHz bus in 130 nm. The 90 nm design features PowerTune for rapid frequency and power scaling and electronic fuses.

Sram Operational Voltage Shifts in the Presence of Gate Oxide Defects in 90 NM SOI

The continued scaling of gate oxide thickness in CMOS transistors has made dielectric integrity paramount to system functionality at low voltages. In this paper, the effect of gate oxide breakdown on the minimum operating voltage (Vddmin) of a six transistor SRAM cell has been examined. A new cell reliability model was developed to explain non-monotonic operational voltage shifts through product reliability stress. Through simulation it was determined that non-monotonic voltage shifts can occur if random gate defects counter existing SRAM cell asymmetries. Furthermore, it has been shown that monotonic voltage shifts can be created with significantly different magnitudes of gate oxide defects

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

A 64B CPU Pair: Dual- and Single-Processor Chips

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the duals basic core and cache design

Circuit Design Margin and Design Variability

In the preceding chapters, process variations and circuits styles were discussed. Each circuit style has its own reaction to variations of the process. Each variation must be accounted for to maintain the functionality and desired speed of the circuit across these distributions. All process parameter distributions are a function of the range that the parameter is critical both spatially and temporally. This chapter will investigate the variation of the process on static CMOS logic, dynamic domino, pass gate and DCVS logic.

SE6 Secure Digital Systems

Digital security has become an essential feature in many modern systems. In 2005 and 2006, nearly one third of the residents of the United States have been informed that their personal or financial data may have been compromised by data breaches, such as the stolen Department of Veterans Affairs computer containing records on 26.5 million personnel. We depend on secure systems for electronic commerce and for the new digital economy. Music and software piracy siphons off tens of billions of dollars a year of revenues from copyright holders, yet poorly designed digital rights management angers consumers and even exposes computers to viruses. Individuals require secure communications for privacy, which is increasingly challenged as major governments monitor their own citizens.

Technology Circuit Co-Design for High Performance Logic

Achieving maximum logic performance at minimum power consumption in deeply scaled CMOS technologies requires the cooperative design of technology, circuits, and architecture. The objective of this paper is to examine the interaction of technology and circuits in highly synchronous logic, and the factors which influence the size of the functionality window and the circuit-limited-yield across process and over time. Specific circuit topology as well as generic chip responses will be explored and tied back to underlying idiosyncrasies of the field effect transistor.