Keith M. Carrig

A new direction in ASIC high-performance clock methodology

This paper describes an effective clock methodology for growing and inserting clock trees on high-performance, low-power ASIC chips. Key attributes of the method are that it does not add unnecessary wire, avoids the noise and power-supply drop associated with localized high-current-density clock circuits, and accounts for high-frequency effects such as inductance. A sophisticated automated balanced router and a special clock buffer circuit allow the methodology to work on a large variety of chip sizes, package types, latch counts, and operating frequencies. The methodology enabled automated creation of entire clock networks, including verification, in less than one day, with less than 100 ps of design system skew on complex ASIC chips.

A clock methodology for high-performance microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

A 300 K-circuit ASIC logic family CAD system

A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent internal representation; optimize them for area, performance, and testability; and translate them to an implementation in the technology circuit library. The synthesis systems add logic circuits needed for testing and generate information about the clock trees used later in physical clock-free construction.<<ETX>>

Pattern Density Methodology Using IBM Foundry Technologies

An overview of important pattern density requirements and tradeoffs for advanced RF, analog and digital technologies is presented. This paper reviews process sensitivities to pattern density, the advantage of pattern density compliant designs, performance and modeling considerations, and presents methods of detecting and enhancing pattern density deficiencies to improve overall manufacturability.

A Clock Methodology for High-Performance Microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips

A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8- mu m, four-level-metal, single-poly CMOS process, with a 0.45- mu m nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip. >

Circuit Design Margin and Design Variability

In the preceding chapters, process variations and circuits styles were discussed. Each circuit style has its own reaction to variations of the process. Each variation must be accounted for to maintain the functionality and desired speed of the circuit across these distributions. All process parameter distributions are a function of the range that the parameter is critical both spatially and temporally. This chapter will investigate the variation of the process on static CMOS logic, dynamic domino, pass gate and DCVS logic.

Slack Borrowing and Time Stealing

With any circuit, clocking, and latching selection, the concept of how to fit more logic within a path between latches than is readily available always becomes an issue. That is, inevitably a logical pipeline partition will require more time than is available, for example, more than a full-cycle time in a master-slave system or a half-cycle in a two-phase separated-latch system. Depending on the circuit style, the latching structure, and the clocking strategy, obtaining this time can be classified as one of two categories, slack borrowing and time stealing (also commonly referred to as cycle stealing).

Non-Clocked Logic Styles

Non-clocked logic is ubiquitous in electronic design, due to a number of considerations including: Low power consumption Straightforward delay rule timing Inherent reliability and noise immunity Process variation and defect tolerance Migratability into successive technology generations. Deterministic diagnostic capability.

Clocked Logic Styles

In the preceeding chapter, nonclocked circuit topologies were shown generally to be versatile, reliable, and relatively low in power consumption. Clocked logic, on the other hand, is recognized for its performance advantages, which may be attributed to the following: 1. In Static CMOS, logic must be built redundantly; circuit operations must be realized in both NFET and PFET device structures to accomodate both up and down logic transitions. This reduces performance by adding gate fan-out load and interconnect RC. Higher device counts lead to longer interconnects, higher power consumption and bigger die1. 2. In static CMOS, even when the redundant structure is off, the added diffusion and overlap capacitive loads increase power and delay. 3. In Static CMOS, PFET devices must drive the same loads as NFET devices, at half the transconductance. This drives PFET devices to generally be 2X the width of NFET devices for balanced transitions. The impact is of particular concern structures such as PFET devices 5 and 6 in Figure 2.2a.