George Jonathan Kluth

Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts

Process for forming fully silicided gates

Single anneal for dopant activation and silicide formation

METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FOM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE

Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device

Double silicide formation in polysicon gate without silicide in source/drain extensions

Integrated circuit having long and short channel metal gate devices and method of manufacture

Fully nickel silicided metal gate with shallow junction formed

METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME

Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface