Chun-Chieh Lin

BEOL process integration of 65nm Cu/low k interconnects

The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive Trameca for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.

Novel Strained-Si Substrate Technology for Transistor Performance Enhancement

Strained-Si channel transistors offer significant perforrnance enhancement. However, most designs based on bulk-Si subsfrates utilize thick SiGe buffer layers or complex multi-layer structures for the intoduction of tensile strain in the Si channel and might not be easily or economically integrated into a conventional cMos process t1]. Various methods to irnplement sfiained-Si subsfrates based on silicon-on-insulator (SOf wafers have also been demonstated [2]-[3], but they suffer from an inherent high cost and process corrplexity. In this paper, we present a new, inexpensive, and manufactuable strained-Si substrate technology based on bulk-Si subsfiate, and demonstrate significant enhancement in fransistor perfonnance.