Chun-Kuang Chen

65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

This paper describes a leading-edge 0.18 /spl mu/m CMOS logic foundry technology. Very aggressive design rules and borderless contacts render a 4.4 /spl mu/m/sup 2/ embedded (synchronous cache) 6T SRAM cell demonstrated in a 1 Mb vehicle with very high yield. Robust dual-gate oxides were developed to support 1.5-2 V core logic as well as 3.3 V periphery (I/O) circuitry. Advanced modular core device technology using 32 /spl Aring/ oxides for 1.8-2 V operation and 27 /spl Aring/ oxides for 1.5-1.7 V applications support competitive high-performance (MPU/graphics) or low-standby power (mobile) applications. Transient-enhanced diffusion is effectively used in I/O devices to enhance hot-carrier lifetime. This is the first 0.18 /spl mu/m technology demonstrating a highly manufacturable 6 to 7 level low-k (HSQ)/AlCu interconnect system with tightest metal pitch (0.46 /spl mu/m M1 and 0.56 /spl mu/m at intermediate levels), as well as aggressive borderless and fully stacked vias without poisoning problems. AlCu/FSG and dual-damascene Cu/oxide interconnect options have also been proven with comparable SRAM yield to the AlCu/HSQ system.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication

A sidewall electrode technology was successfully developed for the first time in this study, improving the understanding of the working mechanism in an ultra small, functional HfO₂-based resistive random access memory (RRAM) device (<; 1 × 3 nm²). This technology exhibits potential for application in atomic-scale memories. The 1 × 3 nm² RRAM device exhibited an excellent performance, featuring a high endurance of more than 10⁴ cycles, a large on/off verified window (>100), and reasonable reliability (stress time > 10³ s, 2 × 10⁴ h at 250 °C). Furthermore, the 1 × 3 nm² RRAM device exhibited distinctive unipolar behavior when a high voltage and rapid switching operation (7 V, 50 ns) were applied, and a switching mechanism model is proposed.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

Characterization of ArF immersion process for production (Invited Paper)

ArF immersion lithography is essential to extend optical lithography. In this study, we characterized the immersion process on production wafers. Key lithographic manufacturing parameters, overlay, CD uniformity, depth of focus (DOF), optical proximity effects (OPE), and defects are reported. Similar device electrical performance between the immersion and the dry wafers assures electrical compatibility with immersion lithography. The yield results on 90-nm Static Random Access Memory (SRAM) chips confirm doubling of DOF by immersion as expected. Poly images of the 65-nm node from a 0.85NA immersion scanner are also shown.

Magnetic thin-film inductors for monolithic integration with CMOS

This paper presents the fabrication, design and electrical performance of magnetic thin-film inductors for monolithic integration with CMOS for DC-DC power conversion. Magnetic core inductors were fabricated using conventional CMOS processes to achieve peak inductance density of 290nH/mm2, quality factor 15 at 150MHz, current density exceeding 11 A/mm2 and coupling coefficient of 0.89 for coupled inductors.

45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

Highest planar HK/MG PFET performance (ION = 790 muA at Ioff = 100 nA, Vdd= 1 V and Lg= 33 nm) has been demonstrated with a gate-first dual-metal CMOS integrated process and proven by functional SRAM cell. Integrating modern stressors without IL re-growth and achieving band edge work function without increasing TINV are two major challenges for gate-first HK/MG processes. In this work, band-edge effective work function has been achieved without increasing TINV. Furthermore, with successful integration of stress techniques like SiGe-S/D, SMT and CESL, not only performance was improved by 30% but also no reliability degradation was observed. Finally, no degradation from decreasing poly-pitch also suggests its good scalability to next generations.

Thin-film optimization strategy in high numerical aperture optical lithography, part 1: principles

The functional dependence of a resist critical dimension (CD) with respect to resist thickness for a general absorptive thin-film stack in the case of oblique incidence is derived analytically with the rigorous electromagnetic theory. Based on obtained results, we discuss those thin-film effects related to CD control, such as the swing effect, bulk effect, etc., especially in the regime of high numerical aperture optical lithography.