Fu-Jye Liang

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

Immersion defect reduction, part II: the formation mechanism and reduction of patterned defects

193-nm immersion lithography is the only choice for the 45-nm logical node at 120-nm half pitch and extendable to 32- and 22-nm nodes. The defect problem is one of the critical issues in immersion technology. In this paper, we provided a methodology to trace the defect source from optical microscope images to its SEM counterparts after exposure. An optimized exposure routing was also proposed to reduce printing defects. The average defect count was reduced from 19.7 to 4.8 ea/wafer.

Defect reduction with special routing for immersion lithography

This letter reports record-breaking low defect counts for immersion lithography, the mechanism for forma- tion of particle-printing defects, and for two new exposure routings to achieve the low defect counts. Both new routings make the slot-scan directions parallel to the field-stepping directions, whereas in the normal routing the two directions are perpendicular to each other. From experimental data, the average defect count for one of the special routings is 4.8 per wafer, while it is 19.7 per wafer for normal routing.

Immersion defect reduction, part I: analysis of water leaks in an immersion scanner

This paper reports the water-leakage mechanism of the immersion hood in an immersion scanner. The proposed static analysis reveals the immersion hood design performance in defect distribution. A dynamic water-leakage model traces the leaked water and identifies its position on the wafer, during exposure. Comparing simulation to experimental results on bare-silicon and resist-coated wafers, the defect type, source of residuals, and critical settings on the immersion system were clearly identified.

Phase-defocus windows for alternating phase shifting mask

We propose a useful methodology, called phase-defocus (P-D) window, to express the mutual dependence of Alt-PSM mask structure and the wafer process window of the pattern-position shift caused by phase error and intensity imbalance. The P-D window was predicted and optimized with a 2-D mask with effective phase and transmission by simulations. We further used rigorous E-M field simulations to correlate the 3-D mask structure to those optimized conditions. Moreover, experiments were performed with four kinds of mask structures and the best Alt-PSM structure was obtained and used to suggest the mask fabrication performance based on P-D window analysis. In order to understand the influence of mask fabrication on patterns with various densities, the common P-D window is proposed. Using the P-D window, the optimized condition was achieved with a maximum process margin for the mask and wafer. In addition, the P-D window is used to quantify the scattering effect coming from the topographical mask and determine the effective 180° for the iso-focal condition.