Chunhui Fan

Tuning of the Schottky barrier height in NiGe/n-Ge using ion-implantation after germanidation technique

In this paper, a method of ion-implantation after germanidation (IAG) has been presented to modulate the Schottky barrier (SB) heights on germanium substrates. Schottky diodes have been fabricated with improved rectifying current curves and larger Ion/Ioff ratio up to 106. A relatively high effective electron barrier height for NiGe/n-Ge has been achieved by the BF2+ IAG technique, which suggests a record-low effective hole barrier height of nearly 0.06 eV. The tuning of SB height can be mainly contributed to the effects of fluorine. In addition, there is a process temperature window between 350 to 450 °C for the drive-in annealing of IAG to obtain optimized SB heights. These results provide the design guidelines for the process integration of germanium based Schottky barrier source/drain metal-oxide-semiconductor field-effect transistors.

Experimental Demonstration of Current Mirrors Based on Silicon Nanowire Transistors for Inversion and Subthreshold Operations

In this brief, the silicon nanowire transistor (SNWT)-based circuits of current mirrors (NWCMs) have been successfully fabricated for the first time. The key figures of merit of current mirrors (CMs) are experimentally studied, including output voltage coefficient (OVC), output resistance, and dc matching error ε. The experimental results indicate that, due to the unique quasi-1-D transport properties of the SNWTs, NWCMs exhibit superior performance than planar metal-oxide-semiconductor-field-effect-transistor-based CMs (PCMs) in the inversion operation region. Furthermore, NWCMs operating in the subthreshold region shows even better performance than PCMs. With the inherent advantages of the gate-all-around structure, the SNWT is very promising for analog and mixed-signal integrated circuits and particularly has its unique potential at subthreshold operation for low-power applications.

New understanding of the statistics of random telegraph noise in Si nanowire transistors - the role of quantum confinement and non-stationary effects

In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted by the quantum confinement in SNWTs, which cannot be fully explained by classical RTN theory. A full quantum RTN model for SNWTs is proposed for fundamental understanding of the experiments. The characteristics of non-stationary RTN in SNWTs under high-field biases are studied for the first time, based on the developed statistical trap-response (STR) characterization method. The trap capture probability is found to be much different from that of the quasi-stationary RTN, leading to large errors in circuit aging prediction if using traditional RTN distributions. These new understandings are critical for robust SNWT circuit design against RTN.

Top-down fabrication of vertical silicon nano-rings based on Poisson diffraction

Vertical Si nano-rings with a uniform thickness of about 100 nm have been fabricated by conventional optical photolithography with a low cost based on Poisson diffraction. Moreover, the roughness of the Si nano-rings can be effectively reduced by sacrificial oxidation. In order to increase the density of the nano-rings, coaxial twin Si nano-rings have been fabricated by the Poisson diffraction method combined with the spacer technique. The thickness of both the inner and outer Si nano-rings is about 60 nm, and the gap between the twin nano-rings is about 100 nm.

Variability investigation of gate-all-around silicon nanowire transistors from top-down approach

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced by diameter-dependent annealing. In addition, the different impacts of the experimentally extracted variation sources in SNWTs on the threshold voltage and on current flucturation is discussed, as well as the variability impact on SNWT based SRAM cells compared with planar SRAM cells.

Self-heating effect and characteristic variability of gate-all-around silicon nanowire transistors for highly-scaled CMOS technology (invited)

This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire

Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger configuration

The deteriorated radiation effects of very deep-sub-micron (VDSM) MOS transistors with multi-finger are experimentally investigated for the first time. The results show that due to the interaction between reverse narrow channel effect and radiation induced edge effect, multi-finger transistors are more sensitive to radiation in comparison with standard MOSFETs. Larger threshold-voltage shift and higher leakage current are observed. The mechanisms responsible for the effects are briefly discussed. The results demonstrate that special radiation hardening technology should be adopted for multi-finger transistors operating in the radiation environment.

Shell Strain Effects on Valence Band Structure and Transport Property in Ge/Si 1-x Ge x Core-Shell Nanowire

education, Beijing 100871, China *Email: gang_du@ime.pku.edu.cn;xyliu@ime.pku.edu.cn Computer Center of Peking University, Beijing 100871, China Introduction To date, Ge NW based devices are of renewed interest owing to higher bulk mobility with good process compatibility. An active area has been improving those NW devices. The realization of core-shell structures with lattice misfit strain offers intriguing chances for improving NW performance. The introduction of strain effects near interfaces can tailor valence band structures. [4] And the optimization of shell materials or compositions during NW heteroepitaxy process is possible to modulate the device property. [2] Si1-xGex as a shell based NW device is demonstrated a high performance recently. [5] However, there is a paucity of theoretical study on the strained device performance with a Si1-xGex shell in core-shell NWs. In this work, we calculate the varied strain induced by thickness or Ge contents in shell via finite element method. Then, the strained valence band structure is computed by full 6×6 Luttinger-Kohn Hamiltonian. [6-7] The hole mobility is calculated using modified Kubo-Greenwood formula. [8] The results can help to be a guideline to design NW FETs with core-shell structures. Simulation Methodology Based on continuum elastic model, [9] the Si1-xGex shell strain energy expression is as follows: