Shuangshuang Pu

New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

Variability investigation of gate-all-around silicon nanowire transistors from top-down approach

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced by diameter-dependent annealing. In addition, the different impacts of the experimentally extracted variation sources in SNWTs on the threshold voltage and on current flucturation is discussed, as well as the variability impact on SNWT based SRAM cells compared with planar SRAM cells.

Self-heating effect and characteristic variability of gate-all-around silicon nanowire transistors for highly-scaled CMOS technology (invited)

This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire This paper discusses self-heating effect and variability behavior of GAA SNWTs. Due to the 1-D nature of nanowire and increased phononboundary scattering in GAA structure, the selfheating effect in SNWTs based on bulk substrate is comparable or even a little bit worse than SOI devices, which may limit the ultimate performance of SNWT-based circuits and thus special design consideration is expected. On the other hand, random variation has become a practical problem at nano-scale. The characteristic variability of SNWTs is experimentally extracted and studied in detail. And the impacts of nanowire LER, the diameter-dependent annealing enhanced nanowire