Zhihua Hao

New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

Top-down fabrication of vertical silicon nano-rings based on Poisson diffraction

Vertical Si nano-rings with a uniform thickness of about 100 nm have been fabricated by conventional optical photolithography with a low cost based on Poisson diffraction. Moreover, the roughness of the Si nano-rings can be effectively reduced by sacrificial oxidation. In order to increase the density of the nano-rings, coaxial twin Si nano-rings have been fabricated by the Poisson diffraction method combined with the spacer technique. The thickness of both the inner and outer Si nano-rings is about 60 nm, and the gap between the twin nano-rings is about 100 nm.

Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.