Craig W. MacNaughton

Characterization of optical proximity correction features

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designers intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designers intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

Using scatterometry to improve process control during the spacer pitch splitting process

In an effort to keep scaling at the speed of Moores law, novel methods are being developed to facilitate advanced semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches beyond the current lithography resolution limit is spacer pitch splitting. This method typically involves patterning a sacrificial gate pattern, then performing a standard spacer deposition and etch back process, after which the sacrificial gate is removed and the remaining spacers themselves are used as the effective mask for the pattern transfer. Some of the key advantages of this process are the ability to create sub-resolution lines and also the improvement in Line Edge Roughness seen on the final pattern. However, there are certain limitations with this process, namely the ability to only pattern lines in one dimension, and also the complexity of the metrology, where the final Critical Dimension result is a function of the litho condition from the sacrificial gate patterning, and also the various film layer depositions as well as the spacer etch back process. Given this complexity, the accurate measurement of not only the spacer width but also the spacer shape is important. In this work we investigate the use of scatterometry techniques to enable these measurements on leading edge devices.

Subnanometer-precision metrology for 100-nm gate linewidth control

The 0.13 micrometer semiconductor manufacturing generation will have transistor gate structures as small as 100 nm, creating a demand for 10 nm gate linewidth control and for measurement precision on the order of 2 nm. This process control requirement is inherently long-term. Therefore, measurement equipment should be able to run days or weeks without significant excursions. The requirement for long-term precision drives both the design and use of measurement equipment. We have found that long-term measurement precision on a single tool may be divided into orthogonal components corresponding to static repeatability, short-term dynamic reproducibility, and long-term stability of the tool. The static component is limited primarily by signal-to-noise ratio, the dynamic component is limited primarily by sample positioning and focusing, and the long-term component is limited primarily by instrument drift and, in the case of monitor wafers, aging of the sample. In this work, we show that each of these components can be reduced to less than 1 nm, 3-sigma, for CD SEM measurements of etched polysilicon gate structures.

Lithography and metrology overlay troubleshooting by advanced query and multivariate analysis

Overlay specifications are getting tighter and lithographic processes come close to their limits. Minimal process changes can lead occasionally to overlay excursions. We explore the use of advanced query and multivariate analysis techniques to address overlay issues in an advanced production environment. We demonstrate the use of advanced query and multivariate analysis techniques in 4 case studies: identifying problem overlay recipes, comparing sources of variation in backend processing, identifying lithography tool issues, and overlay tool monitoring. Due to the large number of possible filter combinations several simple queries were used as starting points in order to explore the existing overlay database in a systematic way. The goal of the systematic evaluation of the available information was to find the most efficient methods to analyze and identify specific overlay problems. During this screening process, device, layer, and exposure tool specific metrics were found. For the most important findings the data filtering was refined in a second stage. Additional sources of information were incorporated for verification and to make correct conclusions. Standardized sets of queries can be used to monitor the lithographic process or to quickly pin point the root causes. It is shown that one can efficiently identify process, tool, and metrology sources of variation.

Reticle defect printability for sub-0.3k1 chromeless phase lithography (CPL) technology

Chromeless Phase Lithography (CPL) with a high NA exposure tool is shown to be an attractive technology solution for the 65nm node. Under strong image enhancement conditions, the traditional definition of minimum defect printability specifications is no longer adequate. This paper investigates defect printability issues for CPL technology. Based on optimized scattering bar OPC treatments through pitch, a set of defect printability quantification (DPQ) patterns was designed. In the DPQ design, a number of defect types have been programmed with progressively increasing defect size from 0.05(l/NA) to 0.3(l/NA). Each defect type and size on the actual CPL reticle were then fully characterized using an advanced CD SEM metrology system, the KLA8450RT with both wafer and reticle capabilities. This is a very critical step for quantifying defect printability, since in order to accurately assess the printability, the defect dimension must be well correlated to the original DPQ design on the reticle. The DPQ reticle was then printed using a high numerical aperture (NA) scanner (ASML /850T) so that it is possible to characterize the defect printability for each of the programmed defects and the impact on CD through pitch. Minimum printable defect (MPD), maximum non-printable defect (MNPD), and critical dimension (CD) variation percentage were used as metrics to characterize the critical defect size and the sensitivity of each defect type. The purpose of this study is to understand the tolerance of the CLM technology to printable defects and establish a realistic and sensible defect specification.