Pradeep Vukkadala

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Abstract. Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Determining local residual stresses from high resolution wafer geometry measurements

Multiple thin film deposition steps are central to most semiconductor device fabrication processes. The residual stresses in these thin films can induce both in-plane and out-of-plane distortions to the wafer. These residual stresses can vary spatially across the wafer, and the residual stress distributions can change between lithography steps. This can result in noncorrectable overlay errors in the lithography processes. In order to develop strategies for minimizing overlay errors due to residual stress-induced distortion, there is a critical need for techniques that allow the distributions of residual stresses in deposited thin films to be characterized with high spatial resolution. In this paper, the application of established analytical methods for extracting local residual stress from wafer geometry measurements (shape) is investigated. Three-dimensional finite-element models were used to generate simulated wafer shapes resulting from nonuniform residual stress distributions in thin-films. The results of these finite element simulations were used to assess the effectiveness of established analytical techniques. Furthermore, the results demonstrated that local mean curvature of the wafer shape is a simple metric that can be used to qualitatively describe local residual stress variation across the wafer. The simulations also demonstrated that when residual stresses varied over scales of tens of millimeters that high spatial resolution (<1 mm) shape measurements were required in order to accurately predict local residual stress.

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Monitoring process-induced focus errors using high-resolution flatness metrology

Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner tooling / chuck signatures is far from trivial. In this paper we will review how the use of flatness metrology in a 22nm manufacturing environment improved our ability to measure focus errors as well as enabled the decoupling of error between tooling and wafer sources. We will also review several examples of experimental datasets demonstrating how this wafer shape measurement technique has provided unique insight to the nature of topography based focus error, as well as provide a valuable learning mechanism for driving improvement in process cycles of learning.

Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Patterned wafer geometry grouping for improved overlay control

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Models to relate wafer geometry measurements to in-plane distortion of wafers

Abstract. Achieving satisfactory overlay is increasingly challenging as feature sizes are reduced and allowable overlay budgets shrink to several nanometers and below. Overlay errors induced by wafer processing, such as film deposition and etching, constitute a meaningful fraction of overlay budgets. Wafer geometry measurements provide the opportunity to quantify stress-induced distortions at the wafer level and provide information that can be used in a feedback mode to alter wafer processing or in a feed-forward mode to set wafer-specific corrections in the lithography tool. In order for such feed-forward schemes based on wafer geometry to be realized, there is a need for mechanics models that relate in-plane distortion of a chucked wafer to the out-of-plane distortion of a wafer in a free state. Here, a simple analytical model is presented that shows the stress-induced component of overlay is correlated to a corrected local wafer slope metric for a wide range of cases. The analytical model is validated via finite element (FE) simulations of wafers with nonuniform stress distributions. Furthermore, FE modeling is used here to examine the effect of the spatial wavelength of stress variation on the connection between slope and the wafer stress-induced component of overlay.