D. Angot

BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level is also evaluated.

Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔNIT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

28nm node bulk vs FDSOI reliability comparison

In this paper, we present TDDB, HCI and BTI reliability characterization of Nfet and Pfet devices issued from FDSOI and bulk 28nm technologies. 28nm FDSOI devices achieve 32% improved performance, 40% reduced power consumption and improved matching. From device level tests, 28nm FDSOI also demonstrates intrinsic reliability behavior similar to 28 bulk devices, giving confidence in the robustness of this technology.

Technology scaling and reliability: Challenges and opportunities

This paper reviews the challenges in reliability degradation and modeling triggered by the unwavering technology scaling. By an adequate modeling and choice of tools, the challenges can be turn out to opportunities to enhance IPs and products performances through an accurate trade-off with reliability.

Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28nm node

We present new reliability features related to the use of a wide range of bulk back biasing in advanced UTBB FDSOI devices. NBTI and HCI stresses were done addressing degradation dependencies vs. bulk bias with the help of TCAD simulations in order to validate our new proposed NBTI physical model in UTBB FDSOI CMOS node.

New insights about oxide breakdown occurrence at circuit level

With device scaling, electric fields across the gate oxide have increased and supply voltages have been reduced not as much as the gate-oxide thickness, intensifying the probability of dielectric breakdown events for transistors. In this context, the more the oxide thickness is reduced, the more the oxide breakdown degradation is progressive. However, the first breakdown event does not always cause a functional failure in digital circuits. As a consequence, relaxation of the predicted lifetime could be accounted at circuit level with respect to the area scaling. First, this paper deals with characterization of soft breakdown events at device level. Post-breakdown degraded parameters and their dispersion are identified and quantified. Then a transistor-level model of breakdown is presented; it handles distributions of Time to Breakdown, breakdown spots localization and parameters degradation (ΔVt, evolution of Id/Is, ΔIg, ΔIdlin ...). This model is implemented in API, it takes into account both BTI and oxide breakdown degradation contributions and is calibrated for a range of breakdown severity used at circuit level. A custom digital circuit has been implemented to measure the impact of multiple oxide breakdowns on static current and oscillation frequency. The theoretical models of multiple oxide breakdown events reproduce properly the experimental behavior. Finally the case of hard breakdown events in a data path is investigated and the impact on percentage errors is discussed.

Interaction between BTI and HCI degradation in High-K devices

In this paper we review experiments combining several types of FET devices degradation modes, including HCI, bias and unbiased BTI. We analyze the nature and localization of defect issued from these degradation processes and derive rules governing interaction between defect generation process, drain polarization dependency on BTI degradation as well as potential BTI contribution to HCI degradation. Consequences of BTI - HCI interaction on WLR analysis as well as product operation will be discussed.

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

Aging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonic degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such as Dielectric Breakdown (DB) are identified as the major sources of reliability hazard. The impact of these phenomena on the digital circuits is usually observed in terms of timing degradations and thus may result in setup/hold violation. In this paper we will focus on the impact of aging related degradation mechanisms on timing. In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warnings prior to timing violation. In this paper, we have developed a dedicated test structure to measure and benchmark the behavior of different monitors. The design of monitors is mostly based on delay elements. Three types of delays are proposed in this paper: flip-flops Master delay, Buffers delay and Passive delay. In addition, we investigate the impact of global and local variations on the accuracy of the measurements by providing complete monitors characterization. The technology used for the test structure and in-situ monitors is 28nm Fully Depleted Silicon On Insulator. Experimental results show a good agreement with SPICE simulation. Finally the proposed in-situ monitors will be compared and their applications to circuit aging prediction will be discussed.

The impact of high V th drifts tail and real workloads on SRAM reliability

Based on experimental measurements at bitcell level combined with SPICE and Monte-Carlo simulations, an analytical method is presented to accurately predict fresh/aged Vmin distributions. The impact of BTI variability modeling and real workloads considerations is also deeply analyzed in this paper.

From BTI variability to product failure rate: A technology scaling perspective

This work provides elements to highlight the reliability challenges related to the technology scaling and the BTI variability. Through main milestones including device reliability scaling model (for both mean and spread), a discussion on the physical origin of BTI variability and a digital IP failure rate analytical model, the evolution of digital IP failure rates along the ITRS scaling roadmap is assessed. and an analysis of the ITRS roadmap on digital IP failure rates. This study offers new perspectives towards product hardening and qualification with respect to both fresh and BTI-related local variability, especially in context where Adaptive Voltage Scaling (AVS) is used to compensate for process centerings.