D. C. Burns

A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator

Abstract An electronically addressed spatial light modulator is introduced. It is based on the hybrid technology of ferroelectric liquid crystal over silicon, and comprises an array of 256 × 256 pixels operating at a charge balanced frame rate of up to 2.1 kHz. The pixel circuit, incorporating a static random access memory latch and an exclusive-OR gate, has significant performance advantages over the single transistor design used elsewhere. The silicon backplane has also been used to help develop post-processing planarisation techniques for high fill-factor (84%), optically flat electrode mirrors.

FERROELECTRIC LIQUID CRYSTAL OVER SILICON SPATIAL LIGHT MODULATOR VIEWABLE UNDER CONTINUOUS ILLUMINATION

We describe a pixel circuit and electronic drive scheme that enables the output of a ferroelectric liquid crystal over silicon spatial light modulator to be viewed under continuous illumination. Th...

Fabrication issues for silicon backplane active matrix miniature liquid crystal display

We describe a new technology which is appropriate for the production of lightweight, highly compact displays. It is based upon a thin layer of ferroelectric liquid crystal (FLC) on top of, and directly driven by, an active matrix backplane fabricated on single crystal silicon. While devices can be produced using fairly standard techniques, we have developed custon fabrication and packaging techniques, required for optimization of optical quality and performance. We have successfully developed the technology for spatial light modulators for use in applications such as optical correlators and programmable holograms. The FLC is configured in the binary surface stabilized configuration: the CMOS circuits are digital in nature. The device operates in reflection with each pixel having an aluminium pad which acts as a mirror to reflect light and as an electorde to control the state of the overlying FLC. The technology also shows promise as a display technology so we have demonstrated the devices as displays capable of displaying both grey scale and color. We have built FLC devices upon commercially fabricated wafers but have found it advantageous to carry out custom post processing order to improve performance. The main thrust to date has been the use of ECR oxide deposition followed by chemical mechanical polishing to provide an optically flat substrate for mirror deposition. This allows the deposition of flat mirrors which fill almost all of the pixel area; it also allows optimization of the mirror deposition for high optical quality and good FLC alignment. Work is also well advanced on a technique to fill the vias connecting to the mirror layer and on packaging devices to reduce bowing of the silicon and increase the thickness uniformity of the FLC layer. Recent results are demonstrated on LCDs fabricated above two silicon backplanes containing 176 X 176 pixels and 256 X 256 pixels respectively, the former having dynamic signal storage at each pixel, the latter static storage.

Post-processing using microfabrication techniques to improve the optical performance of liquid crystal over silicon backplane spatial light modulators

Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.

Ferroelectric liquid crystal over active silicon technology for displays

The structure and principle of operation of a ferroelectric liquid crystal - over - CMOS silicon display are described. Several addressing schemes for creating full color images are introduced and assessed. Preliminary results using 176 X 176 pixel and 512 X 512 pixel DRAM displays are presented.

Advances in pixel design and wafer fabrication for liquid crystal over silicon SLMs

In this paper we will discuss advances in silicon fabrication technology which have allowed the production of liquid crystal over silicon spatial light modulators (LCOS SLMs) with enhanced specification and performance. We will discuss advances in pixel circuit design and VLSI layout, for both DRAM and SRAM based pixels, which have resulted in higher pixel packing density and improved pixel performance. We will illustrate these advances using examples of our most recent SLM designs.

Design and characterisation of an optoelectronic neural chip

Abstract We present a prototype integrated circuit design suitable for use as a neural backplane in an optoelectronic artificial neural network. The device consists of a 4 × 4 array of optical input, electronic output processing elements. The processing elements can sample the temporally multiplexed grey scale generated by a binary mode ferroelectric liquid crystal spatial light modulator. They implement the post-synaptic summing, have a programmable thresholding function, and can respond to both positive and negative activations - a requirement of many artificial neural netork models.