A. O'Hara

Improving the performance of liquid-crystal-over-silicon spatial light modulators:issues and achievements

The performance of liquid-crystal-over-silicon spatial light modulators has advanced rapidly in recent years. Most progress has centered around new device designs with increased bandwidth. In this paper we report on a number of techniques to improve the optical quality; these have applications in both current and future devices.

Mirror quality and efficiency improvements of reflective spatial light modulators by the use of dielectric coatings and chemical-mechanical polishing

To date, silicon backplane spatial light modulators have been characterized by poor-quality mirrors. Hillock formation during metal sintering has been identified as the source of this problem. Here hillock elimination is achieved by constraining the metal with a low-temperature plasma-enhanced chemicalvapor deposition silicon dioxide coating. A double-layer metallization procedure increases the silicon area available for circuitry and improves the mirror fill factor. Second-layer metal mirrors require a flat, intermediate dielectric substrate. Chemical-mechanical polishing is demonstrated to provide the flatness necessary to achieve high optical quality.

A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator

Abstract An electronically addressed spatial light modulator is introduced. It is based on the hybrid technology of ferroelectric liquid crystal over silicon, and comprises an array of 256 × 256 pixels operating at a charge balanced frame rate of up to 2.1 kHz. The pixel circuit, incorporating a static random access memory latch and an exclusive-OR gate, has significant performance advantages over the single transistor design used elsewhere. The silicon backplane has also been used to help develop post-processing planarisation techniques for high fill-factor (84%), optically flat electrode mirrors.

A high resolution, full colour, head mounted ferroelectric liquid crystal-over-silicon display

Abstract The development of a compact, head mounted display based on ferroelectric liquid crystal-over-submicron CMOS technology is described. The reflective display has an array of 1024 × 768 DRAM pixels with aperture ratios of ∼55% (being upgraded to 75%) and covers an area of 12·3mm × 9·2mm providing a resolution of >2000 lines per inch. Colour images are created using time sequential illumination of binary images displayed on the array of DRAM pixels with light from red (660nm), green (525nm) and blue (470nm) pulsed LEDs. The images are projected into the eye over a field of view of 40° diagonal with less than 4% geometrial distortion. Pictures are presented of XGA images with three red, three green, and two blue bit-frames at a frame rate of 1·2KHz (upgrade 2·5KHz) giving 256 colour hues with full 1024 × 768 pixel resolution in each colour (upgrade 216 hues).

A comparative investigation into planarized liquid crystal over silicon spatial light modulators

Abstract Spatial light modulators (SLMs) are arguably the critical elements in coherent optical processing systems. Planarization techniques have been identified as crucial to increasing the performance of ferroelectric liquid crystal over very large scale integration SLMs when used in such systems. Planarization techniques allow enlarged and phase-flat pixel mirrors and improved liquid crystal alignment. This type of SLM is electrically addressed, i.e. transfers electrically represented information into an optical representation via binary phase modulation of the liquid crystal layer by the enlarged pixel modulation mirrors. The backplane design available for use in the study was a 176 × 176 pixel array dynamic random access memory. Investigations show an improvement in the device performance due to the planarization. This improvement was particularly evident when the SLMs were studied operating in a coherent optical system, where the diffraction efficiency was increased. The results compare favourably w...

Test structures for characterising a damascene CMP interconnect process

This paper presents some test structures that can be used to help characterize interconnect fabricated using a CMP damascene process. Electrical measurements of the test structures are compared with those obtained using an AFM and surface profiling.

Test structures for hillock growth, via filling and for measuring the quality of thin films

A test structure for assessing the quality of thin aluminium films is described. An analysis of the relationship between grain structure and hillock growth in small exposed areas of thin films during high temperature processing shows that there is a relationship between hillock growth, grain size and grain boundary structure. The test structure consists of arrays of via holes of various sizes etched in a thin layer of SiO/sub 2/ deposited at low temperature onto the metal surface. After furnace annealing, the number of vias of each size which contain hillocks can be interpreted to obtain information on film quality.

A test structure for the measurement of planarisation

This paper presents simulations of a test structure that can be used to assess the degree of planarisation of inter-layer dielectrics. It consists of sets of comb structures separated by a dielectric. For each structure the combs on the two layers overlap each other with adjacent structures having the overlap in one direction progressionally offset by 0.2 /spl mu/m. The capacitance of these structures is then measured from which the degree of planarisation can be assessed. This structure has potential applications for characterising Chemical Mechanical Polishing (CMP) processes for multi-level VLSI applications.

Fabrication issues for silicon backplane active matrix miniature liquid crystal display

We describe a new technology which is appropriate for the production of lightweight, highly compact displays. It is based upon a thin layer of ferroelectric liquid crystal (FLC) on top of, and directly driven by, an active matrix backplane fabricated on single crystal silicon. While devices can be produced using fairly standard techniques, we have developed custon fabrication and packaging techniques, required for optimization of optical quality and performance. We have successfully developed the technology for spatial light modulators for use in applications such as optical correlators and programmable holograms. The FLC is configured in the binary surface stabilized configuration: the CMOS circuits are digital in nature. The device operates in reflection with each pixel having an aluminium pad which acts as a mirror to reflect light and as an electorde to control the state of the overlying FLC. The technology also shows promise as a display technology so we have demonstrated the devices as displays capable of displaying both grey scale and color. We have built FLC devices upon commercially fabricated wafers but have found it advantageous to carry out custom post processing order to improve performance. The main thrust to date has been the use of ECR oxide deposition followed by chemical mechanical polishing to provide an optically flat substrate for mirror deposition. This allows the deposition of flat mirrors which fill almost all of the pixel area; it also allows optimization of the mirror deposition for high optical quality and good FLC alignment. Work is also well advanced on a technique to fill the vias connecting to the mirror layer and on packaging devices to reduce bowing of the silicon and increase the thickness uniformity of the FLC layer. Recent results are demonstrated on LCDs fabricated above two silicon backplanes containing 176 X 176 pixels and 256 X 256 pixels respectively, the former having dynamic signal storage at each pixel, the latter static storage.

Post-processing using microfabrication techniques to improve the optical performance of liquid crystal over silicon backplane spatial light modulators

Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.