I. D. Rankin

A high resolution, full colour, head mounted ferroelectric liquid crystal-over-silicon display

Abstract The development of a compact, head mounted display based on ferroelectric liquid crystal-over-submicron CMOS technology is described. The reflective display has an array of 1024 × 768 DRAM pixels with aperture ratios of ∼55% (being upgraded to 75%) and covers an area of 12·3mm × 9·2mm providing a resolution of >2000 lines per inch. Colour images are created using time sequential illumination of binary images displayed on the array of DRAM pixels with light from red (660nm), green (525nm) and blue (470nm) pulsed LEDs. The images are projected into the eye over a field of view of 40° diagonal with less than 4% geometrial distortion. Pictures are presented of XGA images with three red, three green, and two blue bit-frames at a frame rate of 1·2KHz (upgrade 2·5KHz) giving 256 colour hues with full 1024 × 768 pixel resolution in each colour (upgrade 216 hues).

Full-color miniature display

Full color images have been demonstrated on a high frame rate, binary, ferroelectric liquid crystal (FLC) display or spatial light modulator (SLM). This display consists of binary surface stabilized ferroelectric liquid (SSFLC) crystal over a custom foundry CMOS silicon VLSI (FLC/VLSI) backplane and provides a new alternative to current well established display technologies. Many issues have been considered to enhance the optical quality of these displays such as the post-processing of the foundry silicon to achieve a high optical flatness and pixel fill factor; with improved liquid crystal alignment. Optimization of electrical addressing schemes and color illumination for video display purposes have been investigated resulting in recommendations for future developments.

Post-processing using microfabrication techniques to improve the optical performance of liquid crystal over silicon backplane spatial light modulators

Liquid crystal (LC) over silicon backplane spatial light modulators (SLMs) have applications in optical processing and as miniature displays. With these devices a LC layer is sandwiched between the silicon backplane and a front cover glass coated with a transparent ITO electrode. The voltage between electrodes on the controlling circuitry and the ITO electrode determines the state of the LC which in turn is used to modulate incident light onto the device. The silicon backplane consists of an array of pixels similar to DRAM or SRAM devices but where each pixel controls the voltage on an electrode. These electrodes must also act as mirrors reflecting the incident light. The silicon backplanes supplied by commercial foundries which work well electrically suffer from having poor optical quality pixel mirrors. These mirrors have inferior surface quality with low flat fill factor resulting in low optical efficiency. Hillocks are also present which cause problems with LC cell construction. We have developed a post-processing procedure based on silicon microfabrication techniques to add another level of metal to commercially fabricated wafers which addresses these problems. To ensure that his new metal layer is deposited onto a very flat substrate the interlevel dielectric is planarized using chemical mechanical polishing. We have developed this technique to produce an optical quality surface with local surface variations of less than 100 angstrom consistently achieved. The deposited aluminium top layer is optimized for best optical performance within the constraints of the electrical characteristics. Pixel mirrors with flat fill factors up to 84% were realized which improved the optical efficiency of the SLM. No hillocks were present on the metal surface presenting the opportunity to fabricate 1 micrometers thick LC cells to fully utilize the potential of ferroelectric LC. We will also report on a n expansion of the post-processing procedure to protect devices based on DRAM memory layout from photo induced charge leakage. The use of microfabrication techniques to construct the LC spacer layer will also be discussed.

Ferroelectric liquid crystal over active silicon technology for displays

The structure and principle of operation of a ferroelectric liquid crystal - over - CMOS silicon display are described. Several addressing schemes for creating full color images are introduced and assessed. Preliminary results using 176 X 176 pixel and 512 X 512 pixel DRAM displays are presented.

FULL COLOUR IMAGES ON A BINARY SPATIAL LIGHT MODULATOR

Abstract Ferroelectric Liquid Crystal over a custom silicon VLSI (FLC/VLSI) backplane technology provides a method of producing low power miniature colour displays. The backplanes are manufactured using a standard silicon wafer foundry process and provides an attractive alternative to current display technologies.