Tomoo Murakami

Flexible heat-flow sensing sheets based on the longitudinal spin Seebeck effect using one-dimensional spin-current conducting films

Heat-flow sensing is expected to be an important technological component of smart thermal management in the future. Conventionally, the thermoelectric (TE) conversion technique, which is based on the Seebeck effect, has been used to measure a heat flow by converting the flow into electric voltage. However, for ubiquitous heat-flow visualization, thin and flexible sensors with extremely low thermal resistance are highly desired. Recently, another type of TE effect, the longitudinal spin Seebeck effect (LSSE), has aroused great interest because the LSSE potentially offers favourable features for TE applications such as simple thin-film device structures. Here we demonstrate an LSSE-based flexible TE sheet that is especially suitable for a heat-flow sensing application. This TE sheet contained a Ni0.2Zn0.3Fe2.5O4 film which was formed on a flexible plastic sheet using a spray-coating method known as “ferrite plating”. The experimental results suggest that the ferrite-plated film, which has a columnar crystal structure aligned perpendicular to the film plane, functions as a unique one-dimensional spin-current conductor suitable for bendable LSSE-based sensors. This newly developed thin TE sheet may be attached to differently shaped heat sources without obstructing an innate heat flux, paving the way to versatile heat-flow measurements and management.

A novel ultra-thin package for embedded high-pin-count LSI supported by Cu plate

We have developed a thin, low-thermal-resistance LSI package by embedding a high-pin-count LSI chip into ultra-thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 µm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics, smaller than 82 µm in the temperature range from −55 to +260 °C. Low thermal resistance of 10.8 °C/W is achieved at a wind velocity of 0 m/s, which is also comparable to that of the FCBGA with a large heat sink. We have successfully demonstrated the functions of this package using an LSI tester and personal-computer-like system board. It has also passed a 600-cycle package-level thermal cycle test.

Electrical design and demonstration of an embedded high-pin-count LSI chip package

Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip chip ball grid array (FCBGA) package using the same chip. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network (PDN) is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick copper plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. Our design for a product LSI chip with approximately 1,500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip.

Enhancement of spin-Seebeck effect by inserting ultra-thin Fe70Cu30 interlayer

We report the longitudinal spin-Seebeck effects (LSSEs) for Pt/Fe70Cu30/BiY2Fe5O12 (BiYIG) and Pt/BiYIG devices. The LSSE voltage was found to be enhanced by inserting an ultra-thin Fe70Cu30 interlayer. This enhancement decays sharply with increasing the Fe70Cu30 thickness, suggesting that it is not due to bulk phenomena, such as a superposition of conventional thermoelectric effects, but due to interface effects related to the Fe70Cu30 interlayer. Combined with control experiments using Pt/Fe70Cu30 devices, we conclude that the enhancement of the LSSE voltage in the Pt/Fe70Cu30/BiYIG devices is attributed to the improvement of the spin-mixing conductance at the Pt/BiYIG interfaces.

Signal-to-Noise Ratio Measurements of Sound Source and Speaker System-in-Package (SiP)

We have developed a system-in-a-package (SiP) consisting of a sound source LSI and a speaker amplifier LSI for mobile applications, and have measured its signal-to-noise ratio (SNR). The sound source LSI chip is stacked on the speaker amplifier LSI chip with inserting a silicon spacer between these chips. Two types of interposers were applied to the SiP: one-metal polyimide tape and a two-metal glass epoxy board. When the output voltage of the speaker LSI was 5 Vp-p, the SNR of the digital-analog converter in the sound source LSI did not change. When it was 15 Vp-p, the SNR was about 1.5 dB worse than with 5 Vp-p. The SNR when the one-metal tape was used was about 1 dB worse than when the two-metal epoxy board was used. The noise source for this degradation was apparently the class-D amplifier in the speaker LSI. These results should be useful in the design for mixed-signal SiPs.

Spin-Seebeck thermoelectric converter

Thermoelectric conversion (TEC) technologies, which convert heat into electricity, have received a great attention, because they are expected to be a powerful approach to utilize wasted thermal energy. Here we present novel thermoelectric converters based on the spin Seebeck effect (SSE), and show their scaling law which is largely different from that of conventional TEC devices. We experimentally demonstrate that the TEC output signals straightforwardly increase with the size of the converters. This scaling law enables us to implement simple-structured thermoelectric converters by using productive film-coating methods. Such coating-based TEC techniques may pave the way for a wide range of applications using a variety of heat sources.

Chip-level and package-level seamless interconnect technologies for advanced packaging

Package-process-oriented thick-Cu-wiring technologies have been developed for forming chip-level and package-level seamless interconnects between an LSI chip and the package substrate. Chip-level seamless interconnects are formed using a resin CMP process. Package-level seamless interconnects are formed by embedding a thinned chip into a resin on Cu base plate. A package with package-level seamless interconnects is thinner and has lower thermal resistance, better power delivery, and finer-pitch interconnects than a conventional flip-chip ball grid array package.

Electrical Design and Techniques for an Embedded High-Pin-Count LSI Chip Package

In order to achieve the excellent electrical performance, as well as low warpage and high heat removal, electrical design techniques for an ultrathin large-scale integration (LSI) package embedding a high-pin-count LSI chip in the thin package substrate have been developed. The embedded chip package we designed is 27 mm × 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip-chip ball grid array package using the same chip, even though the package size is the same. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick Cu plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. In addition, it functioned as a shield component and results in electromagnetic interference suppression. Our design for a fully operative LSI chip with approximately 1500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip. Finally, the advantage of a heat sink connected to ground plane of the package is discussed. It is found that, for excellent near-field noise suppression effects, the heat sink must be connected to the ground plane.