Dan Kuylenstierna

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).

Composite right/left handed transmission line phase shifter using ferroelectric varactors

A composite right/left handed (CRLH) transmission line (TL) phase shifter, using ferroelectric (Ba/sub 0.25/Sr/sub 0.75/TiO/sub 3/) varactors as tunable element, is presented for the first time. It is theoretically and experimentally demonstrated how the unique features of CRLH TLs, enables a differential phase shift with flat frequency dependence around the center frequency. The experimental prototype is a coplanar design integrated on a high resistive Si substrate. It includes four CRLH T-unit cells and has a physical length of 3850/spl mu/m. The ferroelectric varactors are realized in parallel plate version. Under 15-V dc bias applied over each varactor, the differential phase shift is flat around 17GHz and has an absolute value of 50/spl deg/.

60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15mum (fT~ 120 GHz/f MAX> 200 GHz) GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs together with work on packaging (e.g., flip-chip) and system measurements. Compared to the first generation of the designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half the DC power consumption. The system operates with a LO signal in the range of 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO multiplier chain, resulting in an IF center frequency of 2.5 GHz. Packaging and interconnects are discussed and as an alternative to wire bonding, flip-chip assembly tests are presented and discussed. System measurements are also described where bit error rate (BER) and eye diagrams are measured when the presented TX and RX MMICs transmits and receives a modulated signal. A data rate of 1.5 Gb/s with simple ASK modulation was achieved, restricted by the measurement setup rather than the TX and RX MMICs. These tests indicate that the presented MMICs are especially well suited for transmission and reception of wireless signals at data rates of several Gb/s

A Wideband and Compact GaN MMIC Doherty Amplifier for Microwave Link Applications

This paper addresses the limitations and difficulties, in terms of DC-current density restrictions, and process limitations, associated with implementing impedance inverters with high characteristic impedance for monolithic microwave integrated circuit (MMIC) Doherty power amplifiers (DPAs). It is theoretically shown that impedance inverters with high characteristic impedance can be realized by utilizing the output capacitance of the active devices, together with a compact Tee-network of transmission lines with feasible linewidths. The utility of the impedance inverter is proven by design and fabrication of a GaN MMIC-DPA for microwave link applications. Continuous wave (CW) measurements demonstrate a maximum output power of 35±0.5dBm over a frequency range of 6.6-8.5 GHz. The power added efficiency (PAE) in 9 dB output power back-off (OPBO) is better than 30% in a frequency range of 6.7-7.8 GHz. Moreover, linearized modulated measurements, employing a 10 MHz 256-QAM signal with 7.8 dB peak to average power ratio (PAPR), demonstrate higher than 35% average PAE, with 27.5 ± 0.2 dBm average output power, and an adjacent channel power ratio (ACPR) less than -45 dBc, across a 6.8-8.5 GHz frequency range. The fabricated chip-size measures 2.1 mm × 1.5mm.

Lumped-element quadrature power splitters using mixed right/left-handed transmission lines

This paper presents the design of lumped quadrature power splitters (LQPSs) based on unit cells of right-handed (RH) and left-handed (LH) synthetic transmission lines (TLs). The LQPSs include a lumped Wilkinson splitter, with phase-adjusting RH/LH TLs at the outputs. Two topologies, considered to be advantageous with regards to size and electric characteristics, are studied in detail. For these two, closed-form design equations are derived and the performances are analyzed by circuit simulations. The theory and simulation results are experimentally validated by monolithic-microwave integrated-circuit prototypes designed for a center frequency of 2.5 GHz. Both prototypes have performance that agree well with theory and design simulations. Within the frequency range of 2-3 GHz, the maximum amplitude and phase errors are less than 0.3 dB and 3/spl deg/, respectively. All reflections and the isolation are better than -10 dB. The effective areas of the two prototypes are 900/spl times/700 /spl mu/m/sup 2/ and 720/spl times/520 /spl mu/m/sup 2/, respectively.

Ultrawide-band tunable true-time delay lines using ferroelectric varactors

This paper reports on compact tunable true-time delay lines based on ferroelectric (Ba/sub 0.25/Sr/sub 0.75/TiO/sub 3/) varactors integrated on high-resistivity silicon. The delay lines are based on lumped elements, physically implemented as synthetic coplanar-strip lines. An approximate analytical design procedure, exactly valid for /spl omega//spl rarr/0, is proposed. The physical size of the fabricated delay lines is 2.0/spl times/0.33 mm/sup 2/, including bias pads. Measurements are performed from room temperature (RT) down to 80 K. The measurements reveal ultrawide-band characteristics for both group delay and insertion loss. At RT, the absolute group delay is /spl tau//sub /spl delta//(RT, 0 V) /spl ap/70 ps with tunability of 20% under 20-V dc bias, the insertion less than 3.5 dB, and the reflection loss better than 12 dB below 20 GHz. At 145 K, the absolute group delay is increased to /spl tau//sub /spl delta//(145 K, 0 V) /spl ap/100 ps with a tunability of 50% under 20-V applied bias. At 7 GHz, the insertion loss is 3 dB, resulting in figures-of-merit of 0.03 dB/ps and 50 ps/mm. The leakage current at RT is less than 0.1 /spl mu/A.

Calculation of the Performance of Communication Systems From Measured Oscillator Phase Noise

Oscillator phase noise (PN) is one of the major problems that affect the performance of communication systems. In this paper, a direct connection between oscillator measurements, in terms of measured single-side band PN spectrum, and the optimal communication system performance, in terms of the resulting error vector magnitude (EVM) due to PN, is mathematically derived and analyzed. First, a statistical model of the PN, considering the effect of white and colored noise sources, is derived. Then, we utilize this model to derive the modified Bayesian Cramér-Rao bound on PN estimation, and use it to find an EVM bound for the system performance. Based on our analysis, it is found that the influence from different noise regions strongly depends on the communication bandwidth, i.e., the symbol rate. For high symbol rate communication systems, cumulative PN that appears near carrier is of relatively low importance compared to the white PN far from carrier. Our results also show that 1/f 3 noise is more predictable compared to 1/f 2 noise and in a fair comparison it affects the performance less.

On models, bounds, and estimation algorithms for time-varying phase noise

In this paper, a new discrete-time model of phase noise for digital communication systems, based on a continuous-time representation of time-varying phase noise is derived and its statistical characteristics are presented. The proposed phase noise model is shown to be more accurate than the classical Wiener model. Next, using the this model, non-data-aided (NDA) and decision-directed (DD) maximum-likelihood (ML) estimators of time-varying phase noise are derived. To evaluate the performance of the proposed estimators, the Cramér-Rao lower bound (CRLB) for each estimation approach is derived and by using Monte-Carlo simulations it is shown that the mean-square error (MSE) of the proposed estimators converges to the CRLB at moderate signal-to-noise ratios (SNR). Finally, simulation results show that the proposed estimators outperform existing estimation methods as the variance of the phase noise process increases.

Design of broadband lumped element baluns

This paper reports on a small size broadband lumped element balun suitable for integration in MMICs. The design is an extension of the well known lattice balun, which independent of frequency has 180/spl deg/ phase difference between the output ports, but suffers from a narrow amplitude bandwidth. It is shown how the amplitude bandwidth of the lattice balun may be improved by replacing inductors with low-pass T-sections, and the capacitors with high-pass T-sections. Scalable closed-form design equations for various bandwidths are derived. To validate the concept a prototype operating at 1 GHz has been fabricated with SMT chip components soldered on a PTFE laminate. It exhibits amplitude balance better than /spl plusmn/0.25 dB and phase balance better than /spl plusmn/8/spl deg/, over more than one octave bandwidth. The effective chip-area is 7/spl times/9 mm/sup 2/.

Single-Chip 60 GHz Transmitter and Receiver MMICs in a GaAs mHEMT Technology

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15 mum, ~120 GHz fT/> 200 GHz fMAX GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs developed in our group. Compared to our first designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half of the DC power consumption. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (times8) LO chain, resulting in an IF center frequency of 2.5 GHz. The single chip TX MMIC consists of a balanced resistive mixer with an integrated ultra wideband IF balun, a three-stage amplifier and the times8 LO chain. The times8 is a multifunction design by itself consisting of a quadrupler, a feed back amplifier, a doubler, and a buffer amplifier. The TX chip delivers 4.1 plusmn 1.5 dBm over an RF frequency range of 56.5 to 64.5 GHz. The peak output power is 5.6 dBm measured at 60 GHz and the overall TX chip consumes 420 mW of DC power. The single chip RX MMIC contains a three-stage low noise amplifier, an image reject mixer with an integrated ultra wideband IF hybrid and the same times8 as used in the TX chip. The RX chip has more than 10.7 dB gain between 54.5 and 64.5 GHz and more than 13 dB of image rejection ratio between 57.5 and 67.5 GHz with a peak image rejection ratio of 22.5 dB at 64 GHz. The input referred third order intercept point, IIP3 is measured to -10 dBm at 60 GHz and the overall RX chip consumes 450 mW of DC power