Mark C. Foisy

Influence of quantum-well width on device performance of Al/sub 0.30/Ga/sub 0.70/As/In/sub 0.25/Ga/sub 0.75/As (on GaAs) MODFETs

An experimental study in which the quantum well width (W) is varied from 45 to 200 AA is discussed. Optimum device performance was observed at a well width of 120 AA. The 0.2- mu m*130- mu m devices with 120-AA quantum-well width typically exhibit a maximum channel current density of 550 mA/mm, peak transconductance of 550 mS/mm, and peak current gain cutoff frequency (f/sub T/) of 122 GHz. These results have been further improved in subsequent fabrications employing a trilevel-resist mushroom-gate process. The 0.2- mu m*50- mu m devices with mushroom gate exhibit a peak transconductance of 640 mS/mm, peak f/sub T/ of 100 GHz, and best power gains cutoff frequency in excess of 200 GHz. These results are among the best ever reported for GaAs-based FETs and are attributed to the high two-dimensional electron gas (2DEG) sheet density, good low-field mobility, low ohmic contact, and the optimized mushroom gate process. >

Hole Mobility and Thermal Velocity Enhancement for Uniaxial Stress in Si up to 4 GPa

A theoretical study of the response of hole mobility and thermal velocity, both relevant for short channel devices, to [110] uniaxial stress in Si up to 4 GPa of both tension and compression has been conducted. The strained-Si bandstructure was calculated using the kmiddotp method. Effective masses, thermal velocities, and scattering rates were calculated from the bandstructure as a function of stress. Mobilities were then calculated via full band Monte Carlo simulations. Calculated mobilities match experimental and theoretical data from prior work addressing lower degrees of stress. Large increases in both carrier thermal velocities and mobilities were found. In the high-stress regime between 1 and 2 GPa, mobilities exhibit a strong superlinear dependence, and compressive stress becomes more favorable for increasing both mobilities and thermal velocities in pMOS. Improvements in both thermal velocity and mobility finally only begin to rolloff toward apparent saturation as we push the stress toward 4 GPa in these simulations

Multi-Layer Model for Stressor Film Deposition

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.

Enhanced and retarded diffusion of arsenic in silicon by point defect engineering

Arsenic enhanced or retarded diffusion is observed by overlapping the dopant region with, respectively, interstitial-rich and vacancy-rich regions produced by Si implants. Enhanced diffusion can be attributed to interstitial-mediated diffusion during postimplant annealing. Two possible mechanisms for diffusion retardation, interstitial-vacancy recombination and dopant clustering, are analyzed in additional experiments. The point defect engineering approach demonstrated in this letter could be applied to fabrication of n-type ultrashallow junctions.

An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.

Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

Elevated temperature performance of pseudomorphic AlGaAs/InGaAs MODFETs

Parametric DC measurements on pseudomorphic AlGaAs/InGaAs modulation-doped field-effect transistors (MODFETs) were carried out over the 300-405 K temperature range. A gradual channel device model was developed to simulate the temperature dependent behavior and assist in the interpretation of the characteristics. The simulations are shown to provide good predictive ability and confirm the physical reasons why the zero temperature coefficient point of a MODFET occurs only for gate bias voltages below the threshold voltage.

Physically based kinetic Monte Carlo modeling of arsenic-interstitial interaction and arsenic uphill diffusion during ultrashallow junction formation

A kinetic arsenic-interstitial interaction model has been developed to study and predict arsenic transient enhanced diffusion (TED) and deactivation behavior during ultrashallow junction (USJ) formation. This model is based on density functional theory and has been verified by previous experiments in which the significant role of interstitial mechanism in arsenic TED was revealed. The mechanism of enhanced and retarded arsenic diffusion in different point defect environments is investigated by utilizing this model in kinetic Monte Carlo simulation. The arsenic-interstitial pair, with low binding energy and low migration energy, is shown to be the major contributor to arsenic TED in silicon interstitial-rich situations. In addition, by using this model, we demonstrate the transient existence of arsenic-interstitial clusters (AsnIm) during postimplant annealing and propose their possible role in deactivation for short time annealings such as laser annealing and spike annealing. Moreover, we have developed a...

Modeling of short-pulse threshold voltage shifts due to DX centers in Al/sub x/Ga/sub 1-x/As/GaAs and Al/sub x/Ga/sub 1-x/As/In/sub y/Ga/sub 1-y/As MODFET's

The DX-center-related short-pulse threshold voltage shifts (SPTVS) in Al/sub x/Ga/sub 1-x/As-based MODFETs is modeled using CBAND, a simulator that solves Poisson equations self-consistently with Schrodinger equations and donor statistics. Using values given in the literature for the DX energy level in Al/sub x/Ga/sub 1-x/As this technique gives good agreement between measured and simulated SPTVS for Al/sub 0.3/Ga/sub 0.7/As/GaAs and Al/sub 0.3/Ga/sub 0.7/As/In/sub 0.2/Ga/sub 0.8/As MODFETs. Both simulation and experiment show that the use of Al/sub 0.2/Ga/sub 0.8/As in the donor layer reduces the SPTVS relative to the structures using Al/sub 0.3/Ga/sub 0.7/As. However, the measured shifts at this composition are considerably lower than the simulated values, indicating a DX energy level that may be higher than the value extrapolated from the literature, possibly due to the existence of multiple trap levels. Despite this discrepancy, these results support the use of strained-channel layers and lower Al/sub x/Ga/sub 1-x/As compositions in MODFETs for digital and other large-signal applications requiring good threshold stability. >