Davide Sanzogni

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.

A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers

The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs. Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-/spl mu/m CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower. Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV//spl radic/Hz input referred noise voltage density while drawing 4 mA from 1.8 V.

Oxide Breakdown After RF Stress: Experimental Analysis and Effects on Power Amplifier Operation

The target in the design of CMOS radio-frequency (RF) transceivers for wireless application is the highest integration level, despite reliability issues of conventional submicron MOSFETs, due to high RF voltage and current peaks. In this scenario, this paper investigates gate-oxide breakdown under RF stress by using a class-E power amplifier (PA) for experiments. We showed that maximum RF voltage peaks for safe device operation are much larger than usual DC limits, and that the physical mechanism of oxide degradation is triggered by the rms value of oxide field, and not by its maximum, as generally believed. This finding has a strong impact on RF circuit designs, especially in MOSFET scaling perspectives. Finally, breakdown effects on PA operations are discussed

A CMOS direct down-converter with +78dBm minimum IIP2 for 3G cell-phones

A 0.18 /spl mu/m CMOS direct down-converter achieves 78dBm IIP2, 10dBm IIP3, and 4nV//spl radic/Hz noise density. It draws 4mA from a 1.8V supply.

A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication

A 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3 mm2 and consumes 140 mA from 1 V at 8.5 Gb/s.

A 0.13 /spl mu/m CMOS front-end for DCS1800/UMTS/802.11b-g with multi-band positive feedback low noise amplifier

This paper presents a fully-integrated CMOS front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF at 100kHz for DCS 1800. The two key building blocks are a multi-band low noise amplifier that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in 0.13/spl mu/m CMOS process, exhibits a minimum noise figure of 5.2dB, a programmable gain that can be varied from 13.5dB to 28.5dB, an IIP3 of more than -7.5dBm and an IIP2 better than 50dBm. The total current consumption is 20mA from a 1.2 V supply.

An inductor-less 13.5-Gbps 8-mW analog equalizer for multi-channel multi-frequency operation

A low-power analog equalizer has been realized in 45nm CMOS technology. Active feedback is employed to avoid inductors and save chip area. Peaking frequency and gain boost can be finely controlled from 4GHz to 7GHz and from 0dB to 24dB to allow multi-channel multi-frequency operation. The circuit dissipates 8mW from a 1.1V supply and it occupies 0.009mm2. The measured maximum peak-to-peak jitter was 29ps for a 13.5Gb/s data transmission over a 18dB-loss backplane.

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization

Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE) and Duobinary (DB) prove to be effective techniques assuring signal integrity in the presence of ISI, but with speed increase the accuracy of the timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery [1][2][3]. DB alternative may suffer in the presence of long sequences of incoming toggle patterns (1010…). In fact, in DB the channel frequency response is pre-shaped into a target shape, but toggle patterns are converted into a constant level, thus not providing information to the timing loop [2][4].

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR

A 65 nm CMOS receiver including a tapered chain linear equalization and a mixer based clock recovery circuit capable of SSC tracking is presented. The proposed architecture works up to 10 Gb/s with transmission channels with more than 20 dB loss at Nyquist, while consuming 110 mA and occupying 0.25 mm2.

A CMOS direct down-converter with outstanding dynamic range performances

The mechanisms responsible for second order inter-modulation distortion in a direct down-converter are addressed, giving rise to the following design strategy: the transconductor is degenerated by means of an RC filter with pole equal to the signal bandwidth, an LC filter resonating at RF frequency loads the switching pair and carefully matched load resistors develop voltage gain. Prototypes realized in 0.18/spl mu/m CMOS show: +78dBm IIP2 minimum among 40 samples, +10dBm IIP3, 4nV/VHz input-referred noise density while burning only 4mA from 1.8V.