Xiaolei Li

Predictive yield modeling of VLSIC's

This paper presents a comprehensive methodology for predictive modeling of yield losses in modern VLSI technologies. The in-line defect detection and characterization methods are discussed and a new electrical characterization vehicle (CV) methodology is introduced. A complete chip level yield model that takes into account all the defect mechanisms (random and systematic) is presented. We show that extremely good prediction accuracy is achievable if the micro-level yield models are developed taking into account the available redundancy schemes, and the defect density and size distributions are properly extracted from the inline and CV data. Several examples of practical applications of this comprehensive yield methodology are also given.

Predictive yield modeling for reconfigurable memory circuits

This paper presents a novel approach to the modeling of defect related yield losses in reconfigurable memory circuits. The proposed approach is based on the critical area extracted from the memory layout and the in-line defect inspection data. A complete chip level yield model that takes into account the actual redundancy scheme is presented, with the demonstration of excellent accuracy between the model prediction and bitmap data from an actual flash memory product manufactured by Intel Corporation.

Photoresist process optimization for defects using a rigorous lithography simulator

Particulate contamination in photoresist is a major source of yield loss for CMOS processes. Yield loss due to such contamination is controllable by improved filtering. This paper explores the relation between particle size and line spacing for an i-line lithography process using a calibrated defect simulator.

Modeling of defect propagation/growth for yield impact prediction in VLSI manufacturing

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of defect transformation can be applied to early yield impact prediction.

Efficient macromodeling of defect propagation/growth mechanisms in VLSI fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels.

Chip-scale 3D topography synthesis

We propose a novel approach to perform the chip scale mask to topography mapping by building a library of repetitive mask patterns. We call them vicinity patterns. They describe a collection of mask features in close proximity. This pattern library is used to synthesize 3-D topography of an arbitrary part of the chip topography. We define some process-related parameters, which we call critical interaction lengths, as a basis for mask decomposition into the vicinity patterns.

Metropole-3D: a rigorous 3D topography simulator

We have extended the capability of a vector 3D lithography simulator METROPOLE-3D from a photomask simulator to become a full 3D photolithography simulator. It is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwells equations rigorously in three dimensions to model how non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE- 3D consists of several simulation modules: photomask simulator which models the aerial image of any mask pattern (including phase-shifting masks); exposure simulator which models light intensity distribution within the photoresist and arbitrary underlying non-planar substrate structures; post-exposure baking module which models the photo-active compound diffusion, chemically amplified (CA) photoresist cross-linking and de-protection processes; and finally, 3D development module which models the photoresist development process using the level-set algorithm. This simulator has a wide range of applications in studying the pressing engineering problems encountered in state-of-the-art VLSI fabrication processes. The simulator has been applied to the layout printability/manufacturability analysis to study the dominant physical phenomena in lithography, deposition, CMP and etching processes that affect the transfer of mask patterns to the final etched structures on the wafers. Using this new 3D rigorous photolithography simulator, optical proximity effects have been studied. A reflective notching problem caused by the reflective substrate structure has been thoroughly studied, and an anti-reflective coating (ARC) solution to this notching problem has been optimized by the simulations. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

Modeling of defect propagation/growth for early yield impact prediction in VLSI fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of defect transformation can be applied to early yield impact prediction.

The application of submicron lithography defect simulation to IC yield improvement

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach.

The application of lithography defect simulation to submicron CMOS yield improvement efforts

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosing defects. This paper proposes supplementing such experimental work with defect simulation. An example of identifying a defect in the top antireflective coating (TARC) on photoresist illustrates yield improvement efforts involving both defect simulations and experimentation.