Kaidong Xu

Gate double patterning strategies for 10-nm node FinFET devices

Abstract. Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Study of SF6/N2O Microwave Plasma for Surface Texturing of Multicrystalline (<150 µm) Solar Substrates

Surface texturing is an imperative process to reduce the reflection of the incident light on solar cells, by enhancing sunlight diffusion into the silicon solar cells for photon generation. As a result, the current generation can be increased. In this study, the plasma texturing process with linear microwave plasma sources has been benchmarked with the industrial acidic iso-texturing process on 156×156 mm2 multicrystalline substrates. By optimizing the plasma texturing parameters, the absolute solar cells efficiency can be increased by 4.9% for 150 µm thickness silicon substrate. The proposed process offers a significant advantage over the standard acidic iso-texturing without major modification in the existing industrial solar cells manufacturing sequence. In order to explain plasma-induced surface morphology changes, the Kardar–Parisi–Zhang (KPZ), Petri–Brault, and Jason–Drotar models are used.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

Two-Step Plasma-Texturing Process for Multicrystalline Silicon Solar Cells With Linear Microwave Plasma Sources

Surface texturing of crystalline silicon solar cells allows reduction of the reflection of sunlight and enhances photon generation. Plasma-based texturing offers significant advantages over the conventional wet approach, i.e., reduced Si consumption, thin wafer compatibility, increased throughput, and reduced chemical waste. However, it still suffers from insufficient electric yield, i.e., bad performance of plasma-processed solar cells. This paper describes advances made in plasma texturing by means of a linear microwave plasma source. The advantage of a two-step plasma-texturing process is demonstrated, leading to a smoother surface roughness, and resulting in an increased open-circuit voltage, together with a reduced processing time. In addition, the described technology allows a significant reduction of surface damage and could be implemented on a production line for crystalline silicon solar cell manufacturing.

Interconnects scaling challenge for sub-20nm spin torque transfer magnetic random access memory technology

The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.

Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography

In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.

Patterning of 25 nm Contact Holes at 90 nm Pitch: Combination of Line/Space Double Exposure Immersion Lithography and Plasma-Assisted Shrink Technology

In this work, two methods are combined in order to provide 25 nm contact holes at 90 nm pitch: the line/space double exposure immersion lithography and the plasma-assisted shrink technology. We first present the line/space imaging method with negative tone development to create directly 45 nm CH at 90 nm pitch. Then, we discuss plasma-assisted shrink technology and how it applies to these small contacts. Plasma-assisted shrink technology relies on running a fast cyclic process, where plasma polymers are deposited on the photoresist mask, then subsequently redistributed over the features sidewalls, allowing in final a diameter reduction of approximatively 50%. Finally, for the metal-hard-mask patterning approach, the dielectric etch challenges driven by the dimensional scaling are analysed and discussed.