Chi Lim Tan

Statistical spectroscopy of switching traps in deeply scaled vertical poly-Si channel for 3D memories

For future high density storage memories, 3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative because of the extreme reduction of cost per bit (1-3). This architecture, however, faces critical reliability issues related to the highly defective channel (4-5). For instance, we recently showed that discrete current drops and fluctuations (RTN) are clearly observed in the transfer characteristics (ID vs. VG) of these nanoscale vertical nFETs (Fig. 1). These instabilities were linked to single electron trapping/detrapping processes (6-7), which potentially may cause read errors during operation (4-5). The present paper therefore aims at characterizing these adverse switching traps to gain insight into their physical properties. A statistical comparison among different polysilicon channels is presented and benchmarked against monocrystalline planar nFETs. We reveal that a significant part of the switching traps reside in the poly-Si channel.

Laser thermal anneal of polysilicon channel to boost 3D memory performance

We have demonstrated that the engineering of Si channel grains in vertical 3D devices is of tremendous importance for read current, leading to up to 10 times higher ID, 3 times steeper STS slope, tighter ID and STS distributions, better channel-oxide interface, less defective grain boundaries and larger memory window. LTA arises as a potential candidate to engineer the Si channel microstructure. The limitations of LTA regarding crystallization depth can be overcome through complementary techniques such as substrate heating assisted LTA. This learning is crucial for the successful fabrication of advanced vertical devices stacks.

MOVPE In1−xGaxAs high mobility channel for 3-D NAND memory

Epitaxially grown In_1-xGa_xAs is integrated for the first time as replacement of polycrystalline silicon (Si) channel down to 45 nm diameter for 3-D NAND memory application. Channels with different compositions are obtained after careful surface preparation by tuning growth conditions such as: temperature, choice of precursors and flow ratio. In_1-xGa_xAs shows superior conduction properties than poly-Si channel: higher I_on and transconductance (g_m). Potentially good memory operations are also found.

Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing.

In this paper, we investigate the effect of High Pressure Hydrogen or Deuterium Annealing on a vertical charge trapping NAND memory device. Strong improvement is obtained in Vt, subthreshold slope and drive current of the transistors by a better passivation of charge by either species in the bulk ONO memory stack, at the interface between ONO and Poly-Si channel, and in the bulk Poly-Si. Program / Erase and Retention remain identical, and no benefits could be observed by using D2 instead of H2 as passivating species in terms of robustness towards program/erase cycling damages.

Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory

Full channel and Macaroni-type 3-D SONOS memories are thoroughly compared. Macaroni channel provides easier device controllability, resulting in tighter distributions of all electrical characteristics, at the expense of lower channel conduction. Next to this clear trade-off, memory window is also degraded. Improving channel material quality is the way to alleviate the trade-off, as demonstrated by Laser Thermal Anneal treatment of Macaroni channel.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

Feasibility of In x Ga 1– x As High Mobility Channel for 3-D NAND Memory

Epitaxial In_xGa_1-xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate In_xGa_1-xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. In_xGa_1-xAs channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl₂. Thanks to the lower thermal budget involved, Cl₂ seems the most suitable route to preserve the thickness of the TuOx. In_xGa_1-xAs channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher ION and transconductance.

In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.

Stacked-etch induced charge loss in Hybrid Floating Gate cells using high-κ Inter-Gate Dielectric

We investigate the stacked-etch induced charge loss of multi-layer (HfAlO-Al2O3-HfAlO) Inter-Gate Dielectric (IGD) together with a thin Hybrid Floating Gate (HFG), in aggressively scaled planar NAND cells. The results obtained using Bias-Post Program Discharge on no-overlap/overlap capacitors and cells, clearly point out charge loss due to etching damage in Tunnel Oxide (TuOx). On the other hand the inter-gate dielectric damage by stacked etch can be avoided. The etch damage is high with TiN control gate and moderate with amorphous-Si control gate. For short cell featuring Poly-Si control gate, the charge loss occurs through inter-gate dielectric due to the poor interface between inter-gate dielectric / control gate and a degraded intergate dielectric, as suggested by Gate-Side Trap Spectroscopy by Charge Injection and Sensing (GS-TSCIS) and TEM.