Diziana Vangoidsenhoven

Alternative process schemes for double patterning that eliminate the intermediate etch step

Double patterning is used to scale designs below k1 factors that can be obtained with single patterning. Because of the double litho and etch steps, however, this is an expensive and time consuming technique. Spacer defined double patterning, which is commonly used to shrink regular dense patterns as used in memory applications, is an expensive technique because of the many deposition and etch steps that are required. In this paper, we propose several alternative process flows which can reduce the cost-of-ownership by eliminating the intermediate etch step in a double litho, double etch for line/space patterns, and replace it by a process step in the track only. These alternative process flows use thermal freezing resist, positive/negative resist and coating a freezing material. For these materials 32nm node logic patterning can be demonstrated, and even 32nm half pitch can be patterned already with one technique. As alternative technique to spacer defined double patterning, dual tone development is proposed, which can generate pitch doubling in resist using a single exposure. Proof-of-concept of this technique is shown experimentally.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Top coat or no top coat for immersion lithography

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the materials refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the materials dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

The use of unpatterned wafer inspection for immersion lithography defectivity studies

The switch from dry to immersion lithography has important consequences regarding wafer defectivity. It has been shown that for successful and efficient defect reductions related to immersion lithography the capability to distinguish immersion/patterning related defects from stack related defects is very useful during process control. These stack related defects can be observed after careful partitioning of individual layer inspections and the analysis of this data through DSA in Klarity. The optimisation of the dark field inspection SP2 tool, central in this paper, shows that improved sensitivity at adequate signal to noise ratio can be obtained on the resist stacks by using the smaller wavelength as the UV-laser light present in the SP2. For bare Si and BARC oblique incidence illumination gives the best sensitivity and captures the most defects. However monitoring of the resist and stacks with resist requires normal incidence illumination since the nature of defects and film result in a higher scattering intensity using normal illumination. The use of an optical filter and a 10% laser power also contributed to establishing a lower and stable background signal for each inspection scan. As immersion tool development is improved and immersion specific defectivity is reduced, the proportion of the stack related defects will become a significant fraction of the overall target for further defect reduction. This includes point defects (embedded particles) or flow defects (streaks) identified and classified using SURFimage. Finally this information is to be used to identify the defect origin(s) for ultimate elimination of defects in the stacks.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.

Status of ArF lithography for the 130-nm technology node

Lithographers are preparing their processes for the 130nm node. About one year ago, first generation full field ArF step and scan systems have been introduced in a number of fabs. These systems have lenses with numerical apertures in the order of 0.6. At the same time, 0.7 NA KrF step and scan systems have been introduced as well. Also last year, KrF resists were shown to be much more mature than ArF resists.