Steve H. Jen

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

An 802.11g WLAN SoC

A single-chip IEEE 802.11g-compliant WLAN radio that implements all RF, analog, and digital PHY and MAC functions is implemented in a 0.18 /spl mu/m CMOS technology. The IC transmits 4 dBm EVM-compliant output power for a 64QAM OFDM signal. The overall receiver sensitivities are -95 dBm and -73 dBm for data rates 6 Mbit/s and 54 Mbit/s, respectively.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN

A 2.4/5 GHz transceiver implements the RF and analog front-end of an IEEE 802.11a/g/b WLAN system in 0.25 /spl mu/m CMOS technology. The IC transmits 9 dBm/8 dBm EVM-compliant output power at 5 GHz/2.4 GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5 dB at 5/2.4 GHz.

A 1.9GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs

A unified approach for the MOS transistor drain current modeling through all the operation regions is presented. Instead of the direct sum approach, the proposed use of interpolation and sigmoid functions can unify the drain current expression including the drift and diffusion components for the weak- and strong-inversion regions. This approach results in a differentiable continuity in conductances with respect to the gate, drain, and bulk bias voltages. As verified by the experimental data, the model shows an accurate prediction capability for the transconductance and output conductance characteristics in both strong- and weak-inversion regions.

A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply

An efficient MOS transistor charge/capacitance model with continuous expressions for VLSI

A unified modeling approach for the submicron MOS transistor charge/capacitance characteristics in all operation regions is presented. The development of the MOS charge model is based on the charge density approximation to reduce the complexity of the expression. The unified charge densities in gate, channel, and bulk are obtained with assistance of the sigmoid, hyperbola, and exponential interpolation techniques. By carrying out the integration of the charge densities along the channel area, the terminal charges associated with gate and bulk can be obtained. The non-reciprocal capacitance behavior is well realized in this model. Good agreement between the measurement data and simulation results is obtained.

A Unified Approach to Submicron DC MOS Transistor Modelingfor Low-Voltage ICs

A unified single-equation approach for the MOS transistordrain current modeling for energy-efficient submicron MOS circuitsis presented. Instead of three sets of separate equations forthe triode, saturation, and weak inversion regions, only a continuousexpression which is valid to describe the behavior of drain currentand the derivatives in all operation regions can be realizedby using a combination of hyperbola, sigmoid, and interpolationmethods. The model expression can predict accurate results forthe current, output conductance, and transconductance with continuousand smooth characteristics. The simulation results agree wellwith experimental data.

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.

A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained.