Masoud Zargari

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN

A 2.4/5 GHz transceiver implements the RF and analog front-end of an IEEE 802.11a/g/b WLAN system in 0.25 /spl mu/m CMOS technology. The IC transmits 9 dBm/8 dBm EVM-compliant output power at 5 GHz/2.4 GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5 dB at 5/2.4 GHz.

A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

A 5GHz CMOS transceiver for IEEE 802.11a wireless LAN

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN

A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.

Design and implementation of a CMO 802.11n SoC

Wireless local area networks based on the IEEE 802.11 standard are rapidly replacing wires within homes and offices. The latest data-rate amendment to the IEEE 802.11 standard, known as the 802.11n, provides enhanced user experience by exploiting MIMO techniques that use multiple antennas for both transmitter and receiver. In conjunction with MAC layer improvements such as aggregating data, the 802.11n standard supports PHY data rates as high as 600 Mb/s with four spatial streams. This article discusses various MAC and PHY level modifications introduced in 802.11n, as well as the architecture, design trade-offs, and implementation details of a two spatial stream CMOS 802.11n-draft-compliant SoC.

A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.