Johnathan E. Faltermeier

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

Recent Progress and Challenges in Enabling Embedded Si:C Technology

Summary In summary, this work demonstrates that integrating ISPD eSi:C stressor in the thick-oxide long-channel nMOS source and drain is feasible. Key challenges lie in both high-quality ISPD eSi:C EPI development and modification of the conventional Si CMOS fabrication process to preserve eSi:C strain. Acknowledgements This work was performed by IBM/AMD/Freescale Alliance Teams at various IBM Research and Development Facilities. We wish to thank Applied Materials and ASM America for supplying high quality eSi:C EPI materials. References: [1] Kah-Wee Ang, King-Jien Chui, Vladimir Bliznetsov, Yihua Wang, Lai-Yin Wong, Chih-Hang Tung, N. Balasubramanian, Ming-Fu Li, Ganesh Samudra, and Yee-Chia Yeo, IEDM Tech. Dig., p503, 2005.[2] Yaocheng Liu, Oleg Gluschenkov, Jinghong Li, Anita Madan, Ahmet Ozcan, Byeong Kim, Tom Dyer, Ashima Chakravarti, Kevin Chan, Christian Lavoie, Irene Popova, Teresa Pinto, Nivo Rovedo, Zhijiong Luo, Rainer Loesing, William Henson, Ken Rim, Symp. on VLSI Tech., p.44, 2007. [3] P. Grudowski, V. Dhandapani, S. Zollner, D. Goedeke, K. Loiko, D. Tekleab, V. Adams, G. Spencer, H. Desjardins, L. Prabhu, R. Garcia, M. Foisy, D. Theodore, M. Bauer, D. Weeks, S. Thomas, A. Thean, B. White, SOI Conf. Proc., p.17, 2007. [4] Zhibin Ren, G. Pei, J. Li, F. Yang, R. Takalkar, K. Chan, G. Xia, Z. Zhu, A. Madan, T. Pinto, T. Adam, J. Miller, A. Dube, L. Black, J. W. Weijtmans, B. Yang, E. Harley, A. Chakravarti, T. Kanarsky, I. Lauer, D.-G. Park, D. Sadana, and G. Shahidi, Symp. on VLSI Tech., P. 172-173, 2008. [5] A. Madan, J. Li, Z. Ren, F. Yang, E. Harley, T. Adam, R. Loesing, Z. Zhu, T. Pinto, A. Chakravarti, A. Dube, R. Takalkar, J. W. Weijtmans, L. Black, D. Schepis, ECS SiGe and Realted Materials and Devices Symposium, Hawaii, Oct. 2008 (to be published).

Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.