Son Van Nguyen

Progress in the development and understanding of advanced low k and ultralow k dielectrics for very large-scale integrated interconnects—State of the art

The improved performance of the semiconductor microprocessors was achieved for several decades by continuous scaling of the device dimensions while using the same materials for all device generations. At the 0.25 μm technology node, the interconnect of the integrated circuit (IC) became the bottleneck to the improvement of IC performance. One solution was introduction of new materials to reduce the interconnect resistance-capacitance. After the replacement of Al with Cu in 1997, the inter- and intralevel dielectric insulator of the interconnect (ILD), SiO2, was replaced about 7 years later with the low dielectric constant (low-k) SiCOH at the 90 nm node. The subsequent scaling of the devices required the development of ultralow-k porous pSiCOH to maintain the capacitance of the interconnect as low as possible. The composition and porosity of pSiCOH dielectrics affected, among others, the resistance of the dielectrics to damage during integration processing and reduced their mechanical strength, thereby af...

High-density plasma chemical vapor deposition of silicon-based dielectric films for integrated circuits

In this paper, we present and review recent developments in the high-density plasma chemical vapor deposition (HDP CVD) of silicon-based dielectric films, and of films of recent interest in the development of lower-dielectric-constant alternatives. Aspects relevant to the HDP CVD process and using the process to achieve interlevel insulation, gap filling, and planarization are discussed. Results obtained thus far suggest that the process may play an important role in the future fabrication of integrated circuits, provided several metal-contamination and process-integration concerns can be effectively addressed.

Reaction mechanisms of plasma- and thermal-assisted chemical vapor deposition of tetraethylorthosilicate oxide films

Plasma- and thermal-assisted chemical vapor deposited (CVD) tetrathylorthosilicate (TEOS) oxide films were deposited on silicon substrates using a single-wafer reactor. The deposition kinetics of both plasma and thermal CVD processes were studied as a function of temperature. Film properties and bonding structure were analyzed for as-deposited and annealed films using Fourier transform infrared spectroscopy (FTIR), Auger, x-ray photoelectron spectroscopy (XPS), and nuclear reaction analysis (NRA) techniques. The thermal TEOS films were found to be more porous and to contain more hydrogen, but were more conformal than plasma-deposited TEOS films. Without a plasma, thermal temperatures can assist gas-phase reactions between ozone and TEOS (oxidation) to form conformal oxide films at as low as 200°C. With a plasma, both gas-phase and subsequent surface CVD reactions between TEOS, ozone, and oxygen are substantially enhanced, thus result in CVD films with higher quality

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralargescale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

CVD of fluorosilicate glass for ULSI applications

Abstract Interlayer dielectrics are key materials for size reduction and speed enhancement of ultra large scale integrated devices. As intralevel metal spacing is reduced and lower capacitance is required, the choices for inorganic dielectrics are limited, Fluorosilicate glass is a material that is being considered to meet these requirements because it has shown the ability to extend SiO 2 chemical vapor deposition processing. Fluorine addition in a conventional glass improves gap fill while simultaneously lowering the dielectric constant. This paper will review the progress of fluorosilicate glass processing, examine the reliability of these materials, and discuss the role of fluorine in increasing gap fill and lowering the dielectric constant of standard SiO 2 films.

Plasma‐Assisted Chemical Vapor Deposition and Characterization of Boron Nitride Films

Boron nitride films were deposited in a single-wafer plasma enhanced chemical vapor deposition (PECVD) system using two different reactant gas chemistries: (1) dilute diborane (1% B[sub 2]H[sub 6] in nitrogen), nitrogen and ammonia; (2) borazine (B[sub 3]N[sub 3]H[sub 6]), and nitrogen as precursor materials. Variations of deposition rates, thickness uniformities, refractive indexes, wet and plasma dry etch rates, film stress, and electrical properties were studied as a function of the corresponding deposition parameters. Several analytical methods such as Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, nuclear reaction analysis, elastic recoil detection analysis, scanning and transmission electron microscopy were used to study the deposited films. Electrical properties were measured using metal-insulator-metal and metal-insulator-semiconductor structures. The stable boron nitride films do not react with water vapor showing dielectric constant values between 4.0 and 4.7. These good insulators also show promising characteristics for potential applications in high-performance ultralarge scale integration fabrication.

Low-temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM

Significant progress has been made over the past decade in low-temperature plasma-enhanced and thermal chemical vapor deposition (CVD). The progress has occurred in response to the high demands placed on the insulators of multilevel microelectronic circuits because of the continuing reduction in circuit dimensions. High-aspect-ratio gap filling is foremost among these demands, which also include lower processing temperatures and improved dielectric planarization. This paper reviews the history of interlevel and intermetal dielectrics used in microelectronic circuit manufacturing at IBM and the current status of processes used in IBM manufacturing and development lines, and describes the challenges for future memory and logic chip applications.

Substrate Trenching Mechanism during Plasma and Magnetically Enhanced Polysilicon Etching

Plasma and magnetically enhanced reactive ion etching processes with chlorine gas have been developed for subhalf micron polysilicon gate electrode etching (1). In this paper, gate oxide trenching during polysilicon gate etching using chlorine-based reactive ion etching (RIE) and magnetically enhanced reactive ion etching (MERIE) processes is studied in detail. The trenching mechanism was found to be a direct result of off-angle ion bombardment and reflection from the partially etched polysilicon sidewall during plasma etching. The off-angle ion bombardment is caused by the elastic collision between ions and neutrals as ions move across the plasma shealth. Monte-Carlo simulation confirms the angular distribution of ions under most plasma processing conditions. A two-step MERIE process, first with high etch rate and high anisotropy and second with high selectivity to the gate oxide, with low ion-energy bombardment is also developed to minimize the trenching effect during polysilicon-gate etching

Plasma-assisted chemical vapor deposition and characterization of high quality silicon oxide films

Abstract High quality low temperature plasma silicon oxide films were deposited in a single-wafer chemical vapor deposition (CVD) system using very dilute silane (in helium) and nitrous oxide as reactant gases. Variations in the films deposition rate, thickness uniformity, and refractive index were studied as a function of process parameters. The films were also characterized by Fourier transform IR spectroscopy, X-ray photoelectron spectroscopy, electron spin resonance, nuclear reaction analysis for hydrogen, metal-oxide-semiconductor electrical measurement, wet (10:1 buffered HF) and reactive ion etching with CF 4 and CHF 3 + CO 2 gases. Overall, the qualities of plasma-deposited silicon oxide films are comparable with those of high temperature (700–800°C) thermal CVD oxide films and approaching those of thermally grown oxide. However, because of the effect of the initial transient state phenomenon during plasma deposition processing, thin gate quality plasma-enhanced CVD oxide films with low interface states can only be obtained on deposition upon thin oxide surfaces.

Effect of Si—H and N—H bonds on electrical properties of plasma deposited silicon nitride and oxynitride films

Strong correlations were observed between the improvement in the metal-insulator-semiconductor (MIS) (aluminum-nitride-semiconductor) electrical properties of plasma deposited silicon nitride and oxynitride films and their (Si—H/N—H) bonding ratios in the film bulk. Total hydrogen concentration and spin density of all deposited films decreased with post-deposition annealing. Films with more Si—H bonds and stable (Si—H/ N—H) ratios generally have lowerVfb shift, less positive trap charge and higher breakdown dielectric strength. Silicon oxynitride films with refractive indices of 1.75-1.80, as-deposited and after annealing in forming gas (10% H2 + 90% N2) at various temperatures, were found to have stable (Si—H/N—H) bonding ratios, lower silicon dangling bond density, and better MIS electrical properties compared to other plasma deposited nitride and oxynitride films.