David P. Klaus

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET.<<ETX>>

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

An extremely low contact resistivity of 6-7 × 10^-9 Ω·cm² between Ni_0.9Pt_0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

High-

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

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We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

Ultra-low power operation of 0.1 /spl mu/m CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are carried out in a power supply-threshold voltage design space. Experimental results show a ring oscillator delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor=0.01) at 0.4 V. A 20X reduction in power/circuit is achieved at the same performance level as 0.25 /spl mu/m CMOS.<<ETX>>

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

Abstract. A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

An ultra-low power 0.1 /spl mu/m CMOS

In this study, a comprehensive approach towards assessing pattern collapse challenges and solutions for Extreme Ultraviolet Lithography (EUV) resists beyond the 14nm node is undertaken. The fundamental forces that drive pattern deformation are reassessed in order to propose a generalized design criterion for EUV photoresists and aqueous surfactanated rinses. Furthermore, ultimate pattern collapse solutions such as solvent drying utilizing pressurized fluids (supercritical CO2) are exemplified for sub-60nm pitch EUV patterning. In parallel, alternative EUV integration schemes that use a metal-based hardmask (MHM) are studied using a specifically tailored self-assembled monolayer (SAM) to prevent delamination-driven pattern collapse due to resist-hardmask interfacial adhesion failure. Finally, the marginal image transfer of 40nm pitched L/S of ultrathin EUV resist into a SiARC-underlayer stack appears to be gated by the EUV resist resolution limit and the reduced film thickness budget. An alternative method for achieving improved postetch line width roughness (LWR) with an ultrathin MHM-based integration scheme is herein demonstrated.

Pattern transfer of directed self-assembly patterns for CMOS device applications

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].