James J. Bucchignano

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET.<<ETX>>

High-Performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}

An extremely low contact resistivity of 6-7 × 10^-9 Ω·cm² between Ni_0.9Pt_0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

-Channel MOSFETs With High-

A comparison between the conventional dip development process and resist development with ultrasonic agitation at 40 kHz has been conducted for the development of high-resolution resist nanostructures with dimension down to 50 nm. High-resolution commercially available ZEP520 positive electron resist and an in-house epoxy-based negative resist were used in the study. For large area exposure with ultrasonic agitation for resist development, improved resist sensitivity (≈4%) over a dip development process was observed for positive resist and no sensitivity improvement was seen with negative resist. There was also no observable improvement in the measured resist contrast for both positive and negative resist with and without ultrasonic agitation. For resist development in dense arrays or isolated nanostructures, ultrasonic agitation for positive and negative resist development offered faster development rate, more uniformity in resist development and a larger window for exposure dose variation in resist nano...

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This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10^-8 Omega-cm² for both n⁺ and p⁺ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.

Gate Dielectrics and

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

\alpha

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process.<<ETX>>

-Si Passivation

Abstract. A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

In this study, a comprehensive approach towards assessing pattern collapse challenges and solutions for Extreme Ultraviolet Lithography (EUV) resists beyond the 14nm node is undertaken. The fundamental forces that drive pattern deformation are reassessed in order to propose a generalized design criterion for EUV photoresists and aqueous surfactanated rinses. Furthermore, ultimate pattern collapse solutions such as solvent drying utilizing pressurized fluids (supercritical CO2) are exemplified for sub-60nm pitch EUV patterning. In parallel, alternative EUV integration schemes that use a metal-based hardmask (MHM) are studied using a specifically tailored self-assembled monolayer (SAM) to prevent delamination-driven pattern collapse due to resist-hardmask interfacial adhesion failure. Finally, the marginal image transfer of 40nm pitched L/S of ultrathin EUV resist into a SiARC-underlayer stack appears to be gated by the EUV resist resolution limit and the reduced film thickness budget. An alternative method for achieving improved postetch line width roughness (LWR) with an ultrathin MHM-based integration scheme is herein demonstrated.

Ultrasonic and dip resist development processes for 50 nm device fabrication

Protective top coats and top antireflective coatings (ARCs) are frequently used in conjunction with chemically amplified resists. Top coats provide resistance to airborne contamination, and are particularly important where charcoal filtration is not available in the processing area. They are also useful in environments where delay times between process steps are not precisely controlled. Conductive top coats can be used for e-beam applications to reduce charging and image placement errors. Top ARCs are used to reduce reflections at the resist/air interface, thereby lowering the amplitude of the swing curve. All of these materials are applied on top of the photoresist after the postapply bake. In this article we report that depending on the subsequent processing conditions, top coatings can significantly impact the lithographic performance of the photoresist. Alterations in development rate, optical proximity effects, resist profile, and postexposure bake latitude have been observed as a result of processi...