David Shan

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

POWER8™ is a 12-core processor fabricated in IBMs 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

The POWER8 TM processor: Designed for big data, analytics, and cloud environments

POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and todays exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open ecosystem for server innovation.

5.1 POWER8 TM : A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth

The 12-core 649mm2 POWER8™ leverages IBMs 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5-80nm, 2-144nm, 3-288nm, and 3-640nm pitch layers for low-latency communication as well as 2-2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks.

Resonant clock mega-mesh for the IBM z13 TM

The IBM z13TM microprocessor utilizes a large resonant “mega-mesh” global clock distribution saving 50% of the final-stage clock mesh power and 8% of the total chip power in the desired frequency range of 4.5 to 5.5 GHz compared to a simulated, non-resonant base-line design. The mega-mesh is driven by pulsed buffers. Measurement of the mega-meshs robustness is enabled by skew gradients created by programmable delays. The design is implemented in IBMs high-performance 22nm high-k CMOS SOI technology with 17 metal layers [1].

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 TM microprocessor

A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range from 2.5GHz to more than 5GHz. The POWER8 microprocessor is composed of 12 chiplets, each containing a single resonant clock grid for one core and its L2 cache, and a half-frequency, non-resonant clock grid for the L3 cache. The clock grids drive the local clock buffers (LCBs) that in turn drive the latches. The LCBs are gated off to measure the global clock power from the PLL to the LCBs. The resonant core communicates synchronously with the L3, requiring low skew between the domains. The chip was designed in a 22nm SOI process, including two ultra-thick-metal (UTM) layers (3 microns thick) for power distribution, I/O, all long global clock wires, and the resonant clock inductors. The UTM technology reduces wire resistance and simplifies inductor design, but requires accurate transmission line modeling and special routing.

Optimization and modeling of resonant clocking inductors for the POWER8 TM microprocessor

A parameterized model for resonant clocking inductors embedded in a dense power grid was developed using extensive electromagnetic simulations. The resulting model was used to support resonant clock designs for the POWER8TM microprocessor. The model enabled tuning of the inductance attached to each clock sector to optimize its resonant behavior, resulting in a 33% reduction in clock power. Simulations using the model showed excellent agreement with measurement for inductance, Q and global clock power. Inductor to inductor and inductor to flip-chip solder ball interaction was minimized by shielding provided by the dense power grid.