Deniz E. Civay

Insertion strategy for EUV lithography

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

EUV resist performance: current assessment for sub-22-nm half-pitch patterning on NXE:3300

The major challenge for EUV resists at 22 nm half-pitch and below continues to be simultaneously achieving resolution, sensitivity, and line-width roughness (LWR) targets. An ongoing micro-exposure tool (MET) based evaluation of leading resists throughout 2011 shows that incremental progress toward meeting requirements continues apace, with best-of-breed candidates now capable of limiting 19 nm half-pitch resolution at sensitivities near or below 20 mJ/cm2 and LWR below 4 nm 3σ through process window. Evaluation of a selection of leading resists using an ASML NXE:3100 2nd generation full-field exposure tool demonstrates key performance improvements vs. the previous process-of- record (POR) setup resist including enhanced process window at 22 nm half-pitch and better contact hole uniformity. Champion limiting resolution performance for chemically amplified resists at a relaxed sensitivity specification has advanced to 16 nm half-pitch for both MET and full-field exposures.

EUV OPC for the 20-nm node and beyond

Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV) lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.

Deconstructing contact hole CD printing variability in EUV lithography

Lithographic CD printing variability can be easily captured with a CDU measurement, however delineating the most significant sources causing the variability is challenging. In EUV lithography, the resist, reticle, metrology methodology, and stochastics are examples of factors that influence printing variability. Determining the most significant sources of variability in contact hole and via patterning is particularly interesting because the variability can be measured as a function of two tethered dimensions. Contact hole (CH) variability has a direct impact on device performance while via variability affects metal area scaling and design. By studying sources of variability opportunities for improving device performance and scaling can be identified. In this paper, we will examine sources of contact patterning variability in EUV lithography comprehensively using various EUV exposure tools as well as simulation methods. We will present a benchmark of current state of the art materials and patterning methods with the goal of assessing contact hole printability at the limit of 0.33 NA EUV lithography.

Computational study of line tip printability of sub-20-nm technology

This paper illustrates the increasing importance of line tip printing as measured by the size of the weak line tip zone for sub-20nm technology. This paper suggests adding line tip printability into sub-20nm lithography performance metric in addition to the conventional tip-to-tip resolution. This study shows that these two metrics sometimes respond to lithography conditions inversely. The importance of including line tip printability into technology evaluation is demonstrated by comparing LELE optical lithography and EUV lithography. Also, line tip printing with EUV lithography is explored with various illumination conditions and resist developer tones.

EUV and optical lithographic pattern shift at the 5nm node

At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/self-aligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.

EUV telecentricity and shadowing errors impact on process margins

Monte Carlo simulations are used in the semiconductor industry to evaluate variability limits in design rule generation, commonly for interaction between different layers. The variability of the geometry analyzed is determined mainly by the lithography, process and OPC used. Monte Carlo methods for design rule evaluation can provide the requisite level of accuracy, and are suitable for two or more layer interactions because the variations on one can be assumed to be independent of variations on the other(s). The variability parameters and budget utilized in optical Monte Carlo simulations is well-established. With the upcoming implementation of EUV lithography the variability budget will be impacted. EUV has an off-axis illumination angle that complicates the lithography process by causing telecentricity and shadowing errors. Telecentricity errors manifest as a printed feature being shifted relative to the design. The amount the feature is shifted is a function of the pattern density and design. Shadowing is caused by the 3D nature of the mask combined with EUV reflective mask technology. A shadow occurs at feature edges, where the source does not fully illuminate. Telecentricity and shadowing errors, although small at the 10 nm node, will increase in relative size compared to the features printed beyond the 7 nm node. Telecentricity and shadowing errors are complex in nature and can’t be compensated for with a flat bias. These errors unique to EUV are incorporated into Monte Carlo simulations and evaluated against the standard cell design layers. The effect of these variability parameters is evaluated on critical 7 nm node layout clips.

Subresolution assist features in extreme ultraviolet lithography

Abstract. Lithographic critical dimension (CD) printing variability can be easily captured with a CD uniformity measurement; however, minimizing the variability is a challenging task that requires manipulation of many variables. Contact hole variability has a direct impact on device performance, while via variability affects metal area scaling and design. Subresolution assist features (SRAFs) have been used in the past to improve lithographic printing variability. SRAFs enhance the image log slope of nearby features but are not intended to print themselves. The role of SRAFs in extreme ultraviolet is explored here.

7nm node EUV predictive study of mask LER transference to wafer

The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length (ξ), critical exponent (α) and standard deviation of the line edge (σ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated. An experimentally relevant range of the three mask LER variables was explored in these simulations. CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations. A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line.

EUVL back-insertion layout optimization

Extreme ultraviolet lithography (EUVL) is targeted for front-up insertion at advanced technology nodes but will be evaluated for back insertion at more mature nodes. EUVL can put two or more mask levels back on one mask, depending upon what level(s) in the process insertion occurs. In this paper, layout optimization methods are discussed that can be implemented when EUVL back insertion is implemented. The layout optimizations can be focused on improving yield, reliability or density, depending upon the design needs. The proposed methodology modifies the original two or more colored layers and generates an optimized single color EUVL layout design.