Guy Brammertz

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Characterization of defects in 9.7% efficient Cu2ZnSnSe4-CdS-ZnO solar cells

We have fabricated Cu2ZnSnSe4-CdS-ZnO solar cells with a total area efficiency of 9.7%. The absorber layer was fabricated by selenization of sputtered Cu10Sn90, Zn, and Cu multilayers. A large ideality factor of the order of 3 is observed in both illuminated and dark IV-curves, which seems to point in the direction of complex recombination mechanisms such as recombination through fluctuating potentials in the conduction and valence bands of the solar cell structure. A potential barrier of about 135 meV in the device seems to be responsible for an exponential increase of the series resistance at low temperatures, but at room temperature, the effect of this barrier remains relatively small. The free carrier density in the absorber is of the order of 1015 cm−3 and does not vary much as the temperature is decreased.

Capacitance-voltage characterization of GaAs–Al2O3 interfaces

The authors apply the conductance method at 25 and 150°C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains.

Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures

The authors show the implications that the free carrier trapping lifetime has on the capacitance-voltage (CV) characterization method applied to metal-oxide-semiconductor (MOS) structures. It is shown that, whereas the CV characterization method for deducing interface state densities works well for Si, the generally used frequency range of 100Hz–1MHz is much less adapted to GaAs MOS structures. Only interface trapping states in very small portions of the GaAs bandgap are measured with this frequency range, and mainly the very important midgap region is not properly probed. Performing an additional measurement at 150°C on GaAs MOS structures eliminates this problem.

Temperature and frequency dependent electrical characterization of HfO2/InxGa1−xAs interfaces using capacitance-voltage and conductance methods

Electrical properties of metal-oxide-semiconductor capacitors using atomic layer deposited HfO2 on n-type GaAs or InxGa1−xAs (x=0.53, 0.30, 0.15) epitaxial layers were investigated. Capacitance-voltage (CV) measurements indicated large temperature and frequency dispersion at positive gate bias in devices using n-type GaAs and low In content (x=0.30, 0.15) InxGa1−xAs layers, which is significantly reduced for devices using In0.53Ga0.47As. For In0.53Ga0.47As devices, the CV response at negative gate bias is most likely characteristic of an interface state response and may not be indicative of true inversion. The conductance technique on Pd/HfO2/In0.53Ga0.47As/InP shows reductions in interface state densities by In0.53Ga0.47As surface passivation and forming gas annealing (325 °C).

On the interface state density at In0.53Ga0.47As/oxide interfaces

The authors model the capacitance-voltage (CV) behavior of In0.53Ga0.47As metal-oxide-semiconductor (MOS) structures and compare the results to experimental CV-curves. Due to the very low conduction band density of states, ideal III-V MOS structures should present an asymmetric CV behavior, with lower accumulation capacitance on the conduction band side. The absence of this asymmetric CV shape in experimental CV curves points toward the presence of additional states inside the conduction band at the oxide-semiconductor interface. Comparisons between the model and experimental data allow the determination and approximate quantification of a large acceptorlike interface state density above the conduction band edge energy.

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to

By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance-voltage (C-V) behavior of high-mobility substrate metal-oxide-semiconductor (MOS) capacitors. The results are validated with the experimental In0.53Ga0.47As/ high-κ and InP/high-κ (C-V) curves. The simulated C-V and conductance-voltage (G-V) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of In0.53Ga0.47As and InP MOS devices with various high-κ dielectrics, together with the corresponding border trap density inside the high-κ oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods. The border traps, distributed over the thickness of the high- κ oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of 1019 cm-3. Interface and border trap distributions for InP and In0.53Ga0.47As interfaces with high-κ oxides show remarkable similarities on an energy scale relative to the vacuum reference.

\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}

Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use ofhigh mobility channel materials, such as Ge for p-type metal oxide semiconductor pMOS and III/V for n-type metal oxidesemiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxialgrowth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation STI .This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. Thelow topography enables integration of ultrathin high-

and InP Capacitors

The great technological achievements of the Silicon Metal-Oxide-Semiconductor (MOS) system were possible because of the very good electrical quality of the Si-SiO2 interface. H-passivation of dangling bonds at the latter interface can result in interface state densities lower than 10 eVcm. As Si CMOS scaling now slowly approaches the atomic length scale, an extension of the technology roadmap might be possible by replacing the Si with alternative substrates with higher mobility. For nMOS, III-V materials seem to be good candidates, because of their high electron mobility. Unfortunately, III-V/oxide interfaces are not quite as robust as the Si-SiO2 interface and most interfaces present high densities of interface states. In the present contribution we analyze GaAs and InGaAs interfaces. Several characterization methods such as the photoluminescence intensity method and the conductance method at high and /or low substrate temperatures are used to characterize the interface state distribution of several III-V interfaces. The interface state distributions of GaAs and In0.53Ga0.47As interfaces with amorphous high-k oxides are presented. These distributions are, as opposed to Si, characterized by localized peaks in the bandgap, which leads to some difficulties for the different characterization techniques. For GaAs, all amorphous oxide interfaces show two very large and localized peaks at around mid-gap energies. Whereas the interface state density closer to the band edges can be reduced with (NH4)2S-cleaning and Hpassivation, the large mid-gap peaks can not be successfully suppressed using these techniques. As a consequence GaAs-amorphous oxide interfaces can not be inverted. For In0.53Ga0.47As, the interface states show a very asymmetric distribution, with reasonably low density close to the conduction band and a very strong increase of interface state density towards the valence band (Figure 1). The consequences of this distribution are discussed in terms of band bending coupling ratio, the ability to control the band bending at the oxide-semiconductor interface, and the performance of the corresponding nMOSFET devices.

High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Thin epitaxial GaAs films, with thickness varying from 140to1000nm and different Si doping levels, were grown at 650°C by organometallic vapor phase epitaxy on Ge substrates and analyzed by low-temperature photoluminescence (PL) spectroscopy. All spectra of thin GaAs on Ge show two different structures, one narrow band-to-band (B2B) structure at an energy of ∼1.5eV and a broad inner-band-gap (IB) structure at an energy of ∼1.1eV. Small strain in the thin GaAs films causes the B2B structure to be separated into a light-hole and a heavy-hole peak. At 2.5K the good structural quality of the thin GaAs films on Ge can be observed from the narrow excitonic peaks. Peak widths of less than 1meV are measured. GaAs films with thickness smaller than 200nm show B2B PL spectra with characteristics of an n-type doping level of approximately 1018at.∕cm3. This is caused by heavy Ge diffusion from the substrate into the GaAs at the heterointerface between the two materials. The IB structure observed in all films consists ...