Scott M. Mansfield

Lithographic comparison of assist feature design strategies

Subresolution assist features, when used in conjunction with off-axis illumination, have shown great promise for reducing proximity effects while improving lithographic process window. However, these patterns result in an increased emphasis on the mask manufacturing process, primarily in the areas of mask writing and inspection. In choosing a design strategy, one must be careful to account for the mask making capabilities, such as write tool grid size and linearity, along with the lithographic effect of errors in the mask making process. In addition to mask errors, stepper lens aberrations and expected process variations can also have a large influence on design rules. Generally, design tradeoffs must be made to balance the impact of these for the best overall lithographic performance.

TCAD development for lithography resolution enhancement

Advances in lithography have contributed significantly to the advancement of the integrated circuit technology. While nonoptical next-generation lithography (NGL) solutions are being developed, optical lithography continues to be the workhorse for high-throughput very-large-scale integrated (VLSI) lithography. Extending optical lithography to the resolution levels necessary to support today’s aggressive product road maps increasingly requires the use of resolution-enhancement techniques. This paper presents an overview of several resolution-enhancement techniques being developed and implemented in IBM for its leading-edge CMOS logic and memory products.

Level-specific lithography optimization for 1-Gb DRAM

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Lithographic effects of mask critical dimension error

Magnification of mask dimensional error is examined and quantified in terms of the mask error factor (MEF) for line and hole patterns on three types of masks: chrome-on-glass (COG), attenuated phase-shifting mask (PSM) and alternating PSM. The MEF is unity for large features, but increases rapidly when the critical dimension (CD) is less than 0.5 (lambda) /NA for line-space patterns and 0.75 (lambda) /NA for contacts. In general dark-field spaces exhibit higher sensitivity to mask dimensional error than light-field lines. Sensitivity of attenuated PSMs is similar to COG masks, even for applications in which attenuated PSMs provide benefits in process latitude. Alternating PSMs have the lowest MEF values. Although the MEF has only a slight dependence on feature nesting for contacts, dense lines and spaces exhibit markedly higher MEF values than isolated features. The MEF of a 0.35 (lambda) /NA isolated line is 1.6 whereas that of a dense line of the same dimension is 4.3 illumination is effective in reducing the mask error sensitivity of dense lines. Dose variation causes changes in the MEF of contacts but has little effect on line-space features; focus error degrades (increases the value of) the MEF of both pattern types. A high diffusion and low contrast photoresist process also worsens the MEF. Consequences of mask CD error amplification include tightening of mask specification, design grid reduction, shift in optimal mask bias and enhanced defect printability.

Reducing DfM to practice: the lithography manufacturability assessor

The need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. Three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. The importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. The need for extensive experimental calibration and improved simulation accuracy is also highlighted.

Process window OPC for reduced process variability and enhanced yield

As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.

The mask error factor in optical lithography

The primary cause of greater than unity mask error factor (MEF) is degradation of image integrity. Mathematical description of image formation reveals the gradual loss of image shape control by photomask features as the critical dimension decreases below 0.8(/spl lambda//NA). The growing contribution of mask critical dimension error to line-width variation prompts generalization of the conventional two-dimensional (2-D) exposure-defocus window (ED window) to a three-dimensional (3-D) mask-exposure-defocus volume (ED volume), adding mask tolerance to exposure latitude and depth-of-focus as the important parameters of a process. The increase in MEF with feature nesting means that the relative importance of sources of line-width variation changes with pattern pitch. Mask improvement is the most effective means to reduce line-width variation for dense features, but lens quality is the most significant factor affecting line-width control for sparse patterns. The approximately 20% higher MEF of dark-field masks, low MEF of alternating phase-shifting masks, and relatively high MEF of assist features all have ramifications on lithography strategies for printing sparse lines. The MEF does not simply indicate a need for high-quality masks, it also sheds light on the critical areas in which improvements are needed for successful lithography, and the disciplines that need to cooperate for successful device fabrication.

Through-process modeling for design-for-manufacturability applications

In recent years, design for manufacturability (DFM) has become an important focus item of the semiconductor industry and many new DFM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity, and here we explore the role of through-process modeling on DFM applications. Several different DFM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored, and methods to ensure their accuracy presented.

Linewidth variation characterization by spatial decomposition

Characterization of linewidth variation by a three-step methodology is presented. Via electrical linewidth measurement, sources of linewidth variation with distinct spatial signatures are first isolated by spatial analysis. Causes with similar spatial signatures are then separated by contributor-specific measurements. Unanticipated components are lastly identified by examination of the residuals from spatial analysis. Significant sources include photomask error, flare, aberrations, development nonuniformity, and scan direction asymmetry. These components are then synthesized to quantify the contributions from the three modules of the patterning process: photomask, exposure system, and postexposure processing. Although these modules are independent of one another, their effects on linewidth variation may be correlated. Moreover, the contributions of the modules are found to vary with exposure tool, development track, and lithography strategy. The most effective means to reducing the overall linewidth variation depends on the relative importance between these components. Optical proximity correction is efficacious only for a well-controlled process where proximity effect is the predominant cause of linewidth variation.

Optimizing style options for subresolution assist features

Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBMs early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.