Nicole Saulnier

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

BEOL process integration for the 7 nm technology node

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

EUV processing and characterization for BEOL

The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for Excellence in July marked the transition from research to process development using EUV lithography. Early process development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and process capability. This work highlights some key learning from early EUV process development with a focus on identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing. While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern characterization.

48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Comparison of left and right side line edge roughness in lithography

The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Towards production ready processing with a state-of-the-art EUV cluster

EUV lithography is one of the main candidates for enabling the next generation of devices, primarily by enabling a lithography process that reduces complexity, and eventually, cost. IBM has installed the latest tool sets at the IBM EUV Center of Excellence in Albany to accelerate EUV lithography development for production use. Though the EUV cluster is capable of enabling the pitch requirements for the 7nm node, the dimensions in question represent a new regime in defectivity. Additionally, new classes of patterning materials are being explored, for which there is very little known up-front regarding known defect mechanisms. We will discuss the baseline cluster performance and the improvement strategy in terms of defectivity and pattern collapse in this paper by utilizing coater/developer techniques based on the new platform.

Feasibility study of resist slimming for SIT

Wet chemical slimming of resist can enable a resist mandrel for sidewall-image transfer (SIT) by decreasing the mandrel width and smoothing the mandrel sidewalls. This would reduce the cost of the SIT process. Several key metrics are used to compare the traditional etched mandrel and the slimmed resist mandrel, including: process window, critical dimension uniformity, and defectivity. New resists are shown to have larger process windows after slimming than an etched mandrel process while maintaining comparable critical dimension uniformity. The major challenge to the resist mandrel is the profile post-slim.

Comprehensive analysis of line-edge and line-width roughness for EUV lithography

Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.