Martin Burkhardt

Dark Field Double Dipole Lithography (DDL) for back-end-of-line processes

The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25% smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.

Integration of EUV lithography in the fabrication of 22-nm node devices

On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.

Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process

We demonstrate experimentally for the first time the feasibility of applying SMO technology using pixelated illumination. Wafer images of SRAM contact holes were obtained to confirm the feasibility of using SMO for 22nm node lithography. There are still challenges in other areas of SMO integration such as mask build, mask inspection and repair, process modeling, full chip design issues and pixelated illumination, which is the emphasis in this paper. In this first attempt we successfully designed a manufacturable pixelated source and had it fabricated and installed in an exposure tool. The printing result is satisfactory, although there are still some deviations of the wafer image from simulation prediction. Further experiment and modeling of the impact of errors in source design and manufacturing will proceed in more detail. We believe that by tightening all kind of specification and optimizing all procedures will make pixelated illumination a viable technology for 22nm or beyond. Publishers Note: The author listing for this paper has been updated to include Carsten Russ. The PDF has been updated to reflect this change.

Impact of resist blur on MEF, OPC, and CD control

This paper will consider the basic concepts of resist blur in a chemically amplified resist process, and the implications of this blur to lithography. In particular, use of a double Gaussian form for the resist blur will be explored. A simple lithographic model utilizing a double Gaussian resist blur was developed and applied to the rapid calculation of lithographic CDs. A typical gate patterning problem was modeled, both with and without assist features, using several different resist blur functions. The OPC treatment was found to be profoundly affected by the resist blur, especially the long-range component. The MEF of small pitch patterns was a sensitive indicator of the short-range blur. The rapid modeling capability allowed large Monte Carlo simulations to explore CD variation at different pitches, pointing out pitches that were particularly vulnerable to CD variation.

Insertion strategy for EUV lithography

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

Fundamental investigation of negative tone development (NTD) for the 22nm node (and beyond)

In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental materials/process interaction perspective. Several key differences exist between a negative tone develop process and a traditional positive tone develop system. For example, the organic solvent dissolves the unexposed material, while the deprotected resist remains intact. This causes key differences in key patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity. We have carried out fundamental studies to understand these new interactions between developer and remaining resist with negative tone develop systems. We have characterized the dynamic dissolution behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent developers. We have also compared contrast curves, and a fundamental model of image collapse. In addition, we present first results on Optical Proximity Correction (OPC) modeling results of current Negative Tone Develop (NTD) resist/developer systems.

Modeling and experiments of non-telecentric thick mask effects for EUV lithography

Various issues related to non-telecentric mask effects for EUV lithography will be discussed in this paper. First, a raytracing approach will provide a conceptual description as to the nature of non-telecentric thick mask effects, highlighting the behavior of various edge types and corners. Rigorous modeling of these effects are discussed along with a few consequences of improper modeling. A series of simulation and experimental studies are presented to probe both the one- and two-dimensional impact of thick mask effects. It will be shown that a simple constant edge bias appears sufficient for 1D features, but begins to break down when space-widths are less than about 45 nm. Investigation into the impact of corners and small 2D features indicates that a simple edge-based bias also breaks down for edge lengths less than about 60nm. A sample set of rules-based post-OPC HV corrections for 22nm node dimensions are proposed, although based on experimental results, it is concluded that more accurate resist modeling and scanner stability are required before being able to precisely predict and control HV effects. Finally, with some simplifying assumptions, simulation is used to predict the extent of potential HV effects of future EUV imaging systems.

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Mitigation of extreme ultraviolet mask defects by pattern shifting: Method and statistics

Currently the mask blanks used in extreme ultraviolet lithography cannot be fabricated free of defects. A rapid method of determining the optimum placement of mask patterns on the blank to avoid these defects is described. Using this method, the probability of fabricating defect-free masks, when the pattern is (1) randomly placed on the mask blank or (2) positioned optimally to avoid defects, is determined for a variety of integrated circuit designs, defect densities, and defect sizes. In addition to circular defects, oval and clusters of defects are also considered. Finally, simple analytical expressions for the probability of obtaining a defect-free mask in the case of random placement of the mask pattern is presented and compared to Monte Carlo simulations.