Dessislava Nikolova

Scaling silicon photonic switch fabrics for data center interconnection networks

With the rapidly increasing aggregate bandwidth requirements of data centers there is a growing interest in the insertion of optically interconnected networks with high-radix transparent optical switch fabrics. Silicon photonics is a particularly promising and applicable technology due to its small footprint, CMOS compatibility, high bandwidth density, and the potential for nanosecond scale dynamic connectivity. In this paper we analyze the feasibility of building silicon photonic microring based switch fabrics for data center scale optical interconnection networks. We evaluate the scalability of a microring based switch fabric for WDM signals. Critical parameters including crosstalk, insertion loss and switching speed are analyzed, and their sensitivity with respect to device parameters is examined. We show that optimization of physical layer parameters can reduce crosstalk and increase switch fabric scalability. Our analysis indicates that with current state-of-the-art devices, a high radix 128 × 128 silicon photonic single chip switch fabric with tolerable power penalty is feasible. The applicability of silicon photonic microrings for data center switching is further supported via review of microring operations and control demonstrations. The challenges and opportunities for this technology platform are discussed.

Comprehensive Design Space Exploration of Silicon Photonic Interconnects

The paper presents a comprehensive physical layer design and modeling platform for silicon photonic interconnects. The platform is based on explicit closed-form expressions for optical power penalties, derived for both signal-dependent and signal-independent noise contexts. Our models agree well with reported experimental measurements. We show how the modeling approach is used for the design space exploration of silicon photonic links and can be leveraged to optimize the wavelength-division multiplexed (WDM) capacity, evaluate the scalability, and study the sensitivity of the system to key device parameters. We apply the methodology to the design of microring-based silicon photonic links, including an evaluation of the impairments associated with cascaded ring modulators, as well as the spectral distortion and crosstalk effects of demultiplexer ring arrays for nonreturn-to-zero (NRZ) ON-OFF keying (OOK) modulated WDM signals. We show that the total capacity of a chip-to-chip microring-based WDM silicon photonic link designed with recently reported interconnect device parameters can approach 2 Tb/s realized with NRZ-OOK data modulation and 45 wavelengths each modulated at 45 Gb/s.

Single Microring-Based

Realizing small-footprint and energy-efficient optical switching fabrics is of crucial importance to solve the data movement challenges faced by optical interconnection networks. This letter demonstrates silicon photonic 2 × 2 full crossbar switching functionality based on a single microring. The ultracompact device is shown to successfully switch data channels from two input ports simultaneously. Data channels in both the multiple and the same wavelength switching experiments are measured to be error-free. Simulation shows that by optimizing some of the microring parameters crosstalk could be reduced. This letter confirms the applicability of a single microring as a 2 × 2 switch element for on-chip optical interconnects.

2\times 2

The article describes an experimentally validated approach for optimizing wavelength-selective microring filters based on optical signals power penalties. The methodology is used to analyze the performance of WDM links for various bit rates and channel-spacing.

Silicon Photonic Crossbar Switches

Silicon photonic interconnects have been proposed as a solution to address chip I/O communication bottlenecks in multicore architectures. In this paper, we perform comprehensive design exploration of inter-chip photonic links and networking architectures. Because the energy efficiencies of such architectures have been shown to be highly sensitive to link utilization, our design exploration covers designs where sharing occurs. By means of shared buses and silicon photonic switches, link utilizations can be improved. To conduct this exploration, we introduce a modeling methodology that captures not only the physical layer characteristics in terms of link capacity and energy efficiency but also the network utilization of silicon photonic chip-to-chip designs. Our models show that silicon photonic interconnects can sustain very high loads (over 100 Tb/s) with low energy costs (1-2 pJ/bit). On the other hand, resource-sharing architectures typically used to cope with low and sporadic loads come at a relatively high energy cost.

Optimization of microring-based filters for dense WDM silicon photonic interconnects

Integrated photonics offers the possibility of compact, low energy, bandwidth-dense interconnects for large port count spatial optical switches, facilitating flexible and energy efficient data movement in future data communications systems. To achieve widespread adoption, intimate integration with electronics has to be possible, requiring switch design using standard microelectronic foundry processes and available devices. We report on the feasibility of a switch fabric comprised of ubiquitous silicon photonic building blocks, opening the possibility to combine technologies, and materials towards a new path for switch fabric design. Rather than focus on integrating all devices on a single silicon chip die to achieve large port count optical switching, this work shifts the focus towards innovative packaging and integration schemes. In this work, we demonstrate 1×8 and 8×1 microring-based silicon photonic switch building blocks with software control, providing the feasibility of a full 8×8 architecture composed of silicon photonic building blocks. The proposed switch is fully non-blocking, has path-independent insertion loss, low crosstalk, and is straightforward to control. We further analyze this architecture and compare it with other common switching architectures for varying underlying technologies and radices, showing that the proposed architecture favorably scales to very large port counts when considering both crosstalk and architectural footprint. Separating a switch fabric into functional building blocks via multiple photonic integrated circuits offers the advantage of piece-wise manufacturing, packaging, and assembly, potentially reducing the number of optical I/O and electrical contacts on a single die.

Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks

The power penalty due to insertion loss and intra-channel cross talk of multistage silicon photonic microring switches is calculated using the transfer matrix method. The results indicate the feasibility of high-radix switches.

Modular architecture for fully non-blocking silicon photonic switch fabric

Silicon Photonics is emerging as a key technology for high-performance computing interconnects. Yet few tools are available to investigate how to best leverage this technology in current or future computer architectures and, furthermore, how this technology will impact real application workloads. In this paper, we present a multi-layer simulation and modeling software solution -- PhoenixSim. PhoenixSim enables integrated and interactive design space exploration over the physical, networking and application layers. In this paper, we report its general organization and constituting models. We show how the different layers of the tool can be utilized to design and analyze an optical interconnect network for supporting the HPCG (High Performance Conjugate Gradient) benchmark.

Analysis of Silicon Photonic Microring-based Multistage Switches

High radix switches are essential for reducing network latency. A possible way to realize them is by using silicon photonic microrings which have been demonstrated to have small foot prints and very fast switching times. By cascading multiple 2 by 2 switches high radix ones can be achieved. However, the scalability of such microring-resonator based switch fabrics is limited by optical power loss and crosstalk. In this work we employ detailed physical layer device models to determine the scalability of such switches. Our results show that a high radix switch with low cross talk and insertion loss is feasible.

PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects

A wealth of high-bandwidth and energy-efficient silicon photonic devices have been demonstrated in recent years. These represent promising solutions for high-performance computer systems that need to distribute extremely large amounts of data in an energy-efficient manner. Chip-scale optical interconnects that employ novel silicon photonics devices can potentially leapfrog the performance of traditional electronic-interconnected systems. However, the benefits of silicon photonics at a system level have yet to be realized. This chapter reviews methodologies for integrating silicon photonic interconnect technologies with computing systems, including implementation challenges associated with device characteristics. A fully functional co-integrated hardware–software system needs to encompass device functionality, control schema, and software logic seamlessly. Each layer, ranging from individual device characterization, to higher layer control of multiple devices, to arbitration of networks of devices, and ultimately to encapsulation of subsystems to create the entire computing system is explored. Finally, results and implications at each level of the system stack are presented.