Diana Tsvetanova

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Degradation of 248 nm Deep UV Photoresist by Ion Implantation

Wet processes are gaining a renewed interest for removal of high dose ion implanted photoresist (II-PR) in front-end-of-line semiconductor manufacturing because of their excellent selectivity towards the wafer substrate and gate materials. The selection of wet chemistries is supported by an insight into the resist degradation by ion implantation. In this work, different analytical techniques have been applied for in-depth characterization of the chemical changes in 248 nm DUV PR after arsenic implantation. A radical mechanism of resist degradation is proposed involving cross-linking and chain scission reactions. The cross-linking of the resist is dominant especially for high doses and energies. It leads to significant depletion of hydrogen and formation of carbon macroradicals that recombine to form C-C cross-linked crust. Moreover, formation of ab-unsaturated ketonic and/or quinonoid structures by cross-linking reactions is suggested. In addition, the dopant species may provide rigid points in the PR matrix by chemical bonding with the resist. For higher doses and energies further dehydrogenation occurs, which leads to formation of triple bonds in the crust. Different p-conjugated structures are formed in the crust by cross-linking and dehydrogenation reactions. No presence of amorphous carbon in the crust is revealed.

Removal of High-Dose Ion-Implanted 248 nm Deep UV Photoresist Using UV Irradiation and Organic Solvent

Wet processes using organic solvents are gaining a renewed interest for stripping high dose ( ≧ 1 × 10 15 atoms. cm -2 ) ion-implanted photoresist (II-PR) in front-end-of-line semiconductor manufacturing because of their excellent selectivity to ultrashal-low implanted substrates and novel materials. However, the highly cross-linked resist layer (so-called crust), formed on the top and sidewalls of the resist has very limited solubility in organic solvents unlike the underlying nonimplanted resist (bulk). This study investigates the effect of UV pre- and post-treatment on II-PR for enabling its removal by organic solvent. Moreover, the impact of the UV wavelength, dose, and power density on the crust and bulk is presented. Optimal conditions of the UV pre- and post-treatment can be determined. Short ( < 200 nm) and long wavelengths (300-400 nm) at low doses induce more scission of the crust with less cross-linking of the bulk, resulting in higher solubility of the II-PR in organic solvents. Moreover, the short wavelength pretreatment is advised because of its bigger effect on the crust, resulting in significant enhancement of the residue removal. In addition, a post-treatment using short wavelengths has high removal efficiency in contrast to the long wavelengths treatment. Finally, no significant impact of the power density is revealed.

Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry

FinFETs are now widely accepted transistor architecture to replace the two dimensional (2D) metal-oxide-silicon field effect transistors (MOSFETs) into a three dimensional (3D), multi-gate (MG) MOSFETs. The MG FinFETs can be fabricated either on a silicon-on-insulator (SOI) substrate or on a bulk silicon substrate. Both approaches require an advanced patterning not only to improve device performance but also to increase the packing density. Despite the simpler process and the benefit of scaling the fin dimension on an SOI substrate, the Si industry prefers the bulk FinFETS owing to their compatibility with the existing CMOS infrastructure and to the reduced wafer cost. The combination of an advanced patterning such as self-aligned-double-patterning (SADP) and a 1× nm FinFETs device fabrication on a bulk Si substrate poses very challenging geometry constraints for the process integration. In this work, the technical and geometrical challenges of a SADP bulk FinFETs process integration are outlined. Finally, an empirical model to establish robust SADP bulk FinFETs integration is presented.

Optimization of Resist Ash Processes on Si0.45Ge0.55 Substrates for Post Extension-Halo Ion Implantation

Scaled high-performance CMOS devices require introduction of new channel materials such as (strained) SixGe1-x or III/V materials, allowing for improved carrier mobility and drive current. SixGe1-x channels can be readily used in a conventional CMOS flow for achieving low PMOS Vt targets. A thin strained SixGe1-x layer with Si cap is epitaxialy grown on the PMOS active regions before gate patterning [1]. During extension/halo ion implantation, this layer is exposed to several dry ash and clean steps in order to remove the photo resist and dopant residues (fig. 1). The formation of thermally unstable and chemical reactive GeO2 [2] and its Si suboxides should be suppressed in order to avoid junction degradation due to material loss and oxidation. The goal of this work was to assess the effect of post ion implant ash plasma chemistry exposure on Si0.45Ge0.55 substrate oxidation and loss. Therefore a 10 nm blanket Si0.45Ge0.55 epi layer was deposited on (100) Si substrate and exposed to traditional ash plasma’s: 100%FG (forming gas), 10%FG/N2O, 10%FG/O2 in a microwave asher and 2-steps CH3F/O2/N2 in a TCP chamber respectively. No wet clean was done before plasma exposure. Ellipsometry, mass measurements, ATR-FTIR and AR-XPS analysis were carried out. Oxidation of the Si0.45Ge0.55 top layer after plasma exposure can be concluded from simple mass measurements: PRE POST (fig. 2). The high oxygen containing plasma’s shows mass increase whereas the N2O/FG plasma shows negligible mass change as compared to the reference sample. This observation is confirmed by ellipsometric thickness measurements and ATR-FTIR. FTIR data (fig. 3) learn that the most pronounced change in intensity is in the range of 800 – 1250 cm-1 corresponding with the GeOx and Si-O-Si stretching band respectively. A clear trend is visible: the oxidation peaks increase with the amount of oxygen in the plasma. The 100%FG chemistry barely shows oxidation as compared with the reference sample. AR-XPS (fig. 4) allows drawing conclusions on the chemical composition (O, N, Ge, GeO, GeO2 Si, C,...) at the surface and deeper in the Si0.45Ge0.55 substrate by varying the exit angle of the measurement. A surface XPS measurement comparing a reference with a 100%FG and a 2-steps CH3F/O2/N2 exposed sample, confirm the highest amount of O present for the 2-steps CH3F/O2/N2 sample. Remarkable is the fact that the GeO2 content for this sample is significant higher than for the 100%FG sample. Also, the N-content in the FG samples is significantly higher than for the reference sample and the 2-steps CH3F/O2/N2. It can probably be explained by the presence of a (GeON)x layer, blocking the surface from further oxidation [3].

Cleaning Challenges and Solutions for Advanced Technology Nodes

Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm Ge and III-V are being considered. Several aspects of wet processing of these materials and advanced integration schemes are covered.

Influence of the Reference Layer Composition on the Back-End-of-Line Compatibility of Co/Ni-Based Perpendicular Magnetic Tunnel Junction Stacks

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400°C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 Å without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 Å CoFeB polarizer from 125% to 145% for a similar RA product after a 300°C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 Å CoFeBTa reference layer spacer can even withstand annealing at 400°C for 90 min and can retain a TMR value of 100% at RA 10 Ω · μm2, while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.

Experimental Observation of Back-Hopping With Reference Layer Flipping by High-Voltage Pulse in Perpendicular Magnetic Tunnel Junctions

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL.

Dummy design characterization for STI CMP with fixed abrasive

The Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) process has an essential role in the STI module for the fabrication of the Complementary Metal Oxide Semiconductor (CMOS) transistors. Since the 0.13 μm technology node a direct STI CMP approach is used, where an oxide film is polished to remove the topography after trench fill and to clear the active regions stopping on a silicon nitride layer. One of the approaches for direct STI CMP uses a Fixed Abrasive (FA) web, which provides excellent planarity. Dummy structures are implemented in the device manufacturing layouts in order to overcome the effect of the different patterned densities and feature sizes. The design of the dummy structures plays a critical role for the CMP performance. In this work, a detailed characterization of the impact of the dummy design on the STI CMP performance using FA has been performed. Based on it, CMP optimized dummy designs have been found. The optimum dummy designs are vertical lines with higher patterned density (PD ~> 30 %) and smaller spacing in y (<; 1 μm) as well as segmented squares with bigger size (x = 5 μm, y = 5 μm, s = 1 μm), higher PD (-> 23 %) and smaller width and spacing of the lines.

Non-Oxidizing Solvent-Based Strip of Ion Implanted Photoresist

The removal of ion implanted photoresist (II-PR) after implantation of ultra shallow extension and halo regions is considered as one of the most challenging front-end-of-line (FEOL) processing steps for 32nm and beyond CMOS technology nodes. Commonly used resist strip processes such as fluorine-based dry plasma ash and hot sulfuric/peroxide mixtures induce unacceptable levels of oxidation and material loss [1-.