Geert Mannaert

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates

Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.

Manufacturing Challenges of GaN-on-Si HEMTs in a 200 mm CMOS Fab

In this paper, we report on the challenges related to growth and processing of 200 mm GaN-on-Si wafers in a CMOS fab. We describe the Au free process we developed as well as how we assure wafer quality prior processing. For the first time, we analyze possible Ga contamination issues related to the processing of GaN wafers and we present the cleaning procedures we developed to avoid it.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si<inf>45</inf>Ge<inf>55</inf>/Si cap deposition and the workfunction metal, high performance devices with balanced V<inf>t,sat</inf> (+0.12V, −0.16V) at scaled T<inf>inv</inf>∼1nm and gate length L<inf>g</inf>∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (Vt, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

Optimization of Resist Ash Processes on Si0.45Ge0.55 Substrates for Post Extension-Halo Ion Implantation

Scaled high-performance CMOS devices require introduction of new channel materials such as (strained) SixGe1-x or III/V materials, allowing for improved carrier mobility and drive current. SixGe1-x channels can be readily used in a conventional CMOS flow for achieving low PMOS Vt targets. A thin strained SixGe1-x layer with Si cap is epitaxialy grown on the PMOS active regions before gate patterning [1]. During extension/halo ion implantation, this layer is exposed to several dry ash and clean steps in order to remove the photo resist and dopant residues (fig. 1). The formation of thermally unstable and chemical reactive GeO2 [2] and its Si suboxides should be suppressed in order to avoid junction degradation due to material loss and oxidation. The goal of this work was to assess the effect of post ion implant ash plasma chemistry exposure on Si0.45Ge0.55 substrate oxidation and loss. Therefore a 10 nm blanket Si0.45Ge0.55 epi layer was deposited on (100) Si substrate and exposed to traditional ash plasma’s: 100%FG (forming gas), 10%FG/N2O, 10%FG/O2 in a microwave asher and 2-steps CH3F/O2/N2 in a TCP chamber respectively. No wet clean was done before plasma exposure. Ellipsometry, mass measurements, ATR-FTIR and AR-XPS analysis were carried out. Oxidation of the Si0.45Ge0.55 top layer after plasma exposure can be concluded from simple mass measurements: PRE POST (fig. 2). The high oxygen containing plasma’s shows mass increase whereas the N2O/FG plasma shows negligible mass change as compared to the reference sample. This observation is confirmed by ellipsometric thickness measurements and ATR-FTIR. FTIR data (fig. 3) learn that the most pronounced change in intensity is in the range of 800 – 1250 cm-1 corresponding with the GeOx and Si-O-Si stretching band respectively. A clear trend is visible: the oxidation peaks increase with the amount of oxygen in the plasma. The 100%FG chemistry barely shows oxidation as compared with the reference sample. AR-XPS (fig. 4) allows drawing conclusions on the chemical composition (O, N, Ge, GeO, GeO2 Si, C,...) at the surface and deeper in the Si0.45Ge0.55 substrate by varying the exit angle of the measurement. A surface XPS measurement comparing a reference with a 100%FG and a 2-steps CH3F/O2/N2 exposed sample, confirm the highest amount of O present for the 2-steps CH3F/O2/N2 sample. Remarkable is the fact that the GeO2 content for this sample is significant higher than for the 100%FG sample. Also, the N-content in the FG samples is significantly higher than for the reference sample and the 2-steps CH3F/O2/N2. It can probably be explained by the presence of a (GeON)x layer, blocking the surface from further oxidation [3].

Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm² on Si:P and ∼2.0×10–9 Ω·cm² on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

For the first time, we have established a replacement metal gate complementary metal-oxide-semiconductor process flow for the high temperature ion implantation of bulk Si fin field-effect-transistors on a 45-nm fin pitch design rule, using high temperature spin-on-carbon hard mask and a dedicated patterning process. In this paper, the advantages of high temperature ion implantation and a detailed process flow of the dedicated patterning are explained. Electrical characteristics of metal-oxide-semiconductor field-effect-transistors and ring oscillators are evaluated.